搜索资源列表
16bit-CLA
- 16 bit carry look ahead adder verilog code
16Bit
- 16Bit Group Ripple Adder ，protel基础的实验模拟-16Bit Group Ripple Adder, protel simulation-based experiment
ADDER
- simple 16-bit CSA Adder
flowvhdl
- 16 bit adder source code.
wallace
- wallace tree 用于16位乘法器的verilog 的 wallace tree代码 -wallace tree verilog file. 16bit wallace tree adder.
adder_csa
- carry select adder in verilog
16bit-CLA
- a 16 bit carry look ahead adder verilog code
full-add-16bit
- full adder 16bit..it s okie
PROJECT1-20130414-20130512
- 16bit adder的verilog源代码和4bit的计数器源代码-source code for 16bit adder and 4bit counter
16bit-ALU
- 16位ALU。包括超前进位加减法器、大小比较、算术逻辑位移等运算-16-bit ALU. Including lookahead adder-subtractor, size comparison, arithmetic and logic operations displacement
adder16.v
- 这是自己写的16bit ripple 形式的加法器的代码，用verilog写的，如果有用，fell free to download-This is to write 16bit ripple adder form of code, verilog written, if useful, fell free to download
HW-02-13210140
- Verilog code adder for add 2 16bit in parallel-adder for 16bit used to add two bits in parallel. this code in verilog languanger
16Bit-Group-Ripple-Adder
- Verilog Testbench for 16Bit Group Ripple Adder
cla_16bit
- verilog 16bit carry lookahead adder-verilog 16bit carry lookahead adder
adder
- 用hspice写了一个做了16bit kogge stone四层点操作的树形加法器静态逻辑网表，所有管子的尺寸按照0.25u的尺寸设计挂上测试文件跑以后逻辑没问题，但是按照拉贝尔那本书上讲的关于逻辑努力优化的方法优化，在输入级加了两级buffer，只对最长路径支路尺寸优化(Use HSPICE to write a 16bit kogge made stone four layer tree adder static logic netlist, all pipe sizes according