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DDS.rar
- DDS信号发生器，利用VHDL实现，可根据频率控制字的改变输出不同频率的信号，最高可到达10MBPS,DDS signal generator, the use of VHDL realization of frequency control word in accordance with changes in output signals of different frequencies, the maximum arrival 10MBPS
FPGA-DDS-FM.rar
- DDS 调频信号发生器框图设计原理，有仿真测试结果,DDS signal generator FM Design Principle diagram
51-DDS
- 基于51单片机 DDS 的信号发生器设计 （有源代码）-51 MCU-based design of DDS signal generator (source code)
dds
- dds signal generator with at90s2313
dds
- 基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode
DDS
- dds 正弦信号发生器步进100HZ 最高频率可达900kHZ 最低频率可大2.3Khz-dds signal generator sin walingbeam 100HZ
dds
- dds信号发生系统 有电路图和程序 希望对大家有帮助-dds signal circuit system and procedures, we hope to help
dds
- dds信号发生器，硬件测试过，效果良好。文件包含整个fpga开发过程产生的所有文件-dds signal generator, the hardware tested to good effect. File contains the entire fpga development process of all documents generated
DDS
- 这是一个用单片机驱动DDS信号发生器的程序-This is a DDS signal generator with a single chip driver program
FPGA_DDS
- 基于FPGA的DDS信号发生器产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-FPGA-based VHDL source DDS signal generator and the test stimulus file matlab model simulation in modelsim adopted under
DDS
- 基于DDS的信号发生器的设计，采用LCD进行显示。-Based on the design of DDS signal generator, with LCD display.
51_mcu_DDS_signal_generator
- 该文件时基于单片机的DDS函数信号发生器，产生的波形为三种：三角波，正弦波，方波-The document function based on single chip DDS signal generator, waveform generated three types: triangle wave, sine wave, square wave
DDS
- Verilog语言实现基于DDS技术的余弦信号发生器，输出位宽16Bit-Verilog language technology based on the cosine DDS signal generator, the output bit width 16Bit
dds
- DDS信号的产生程序，以及DDS相关文章，综合报告。-DDS signal generation procedures and the DDS articles, comprehensive reports.
FPGA-DDS-signal-source-design
- FPGA实现dds的编程，很直观详细的资料-FPGA DDS signal source design
DDS 信号模块AD9850模块资料
- DDS 信号模块 AD9850 模块资料(DDS signal module, AD9850 module data)
四通道DDS信号发生器
- 四通道DDS信号发生器，很好用的代码，大家一起分享(Four-channel DDS signal generator)
DDS
- 用verilog语言，在fpga上实现dds信号发生器，并在vga上显示出来(Verilog realizes DDS Signal Generator)
DDS
- 描述了verilog实现的DDS信号发生器，可以经过FPGA验证，包括了代码实现以及书写。代码可以经过altera的EDA工具进行了验证，可以实现信号发生器的基本功能。希望大家珍惜，并好好学习。(Describes the Verilog implementation of the DDS signal generator, which can be verified by FPGA, including code implementation and writing. Code can be
DDS
- 基于FPGA的DDS信号发生器，可产生频率可调的正弦波(DDS signal generator based on FPGA)