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rtl_DRAM
- 本程式為使用Verilog語言寫控制DRAM的控制模塊, 可以簡易的控制DRAM IC, 本程式已經過系統驗證.-program for the use of the Verilog language to write the control of DRAM control module, be easy to control DRAM IC, the program has been systematically verified.
ref-ddr-sdram-verilog.zip
- sdram的verilog的源码实现,sdram verilog source code realizes
sdr_c_trl_verilog
- SDRAM 控制器的Verilog代码 经过综合验证过的.无截压密码-SDRAM controller Verilog code comprehensive test after all. No cut-off pressure Password
dram_cntl
- DRAM Controller verilog file
t4
- Explain the very good teaching Ve failed to translate miller overall lack of success of verilog language miller decoding Miller verilog language decoder o 4 Multiplier VHDL language design DRAM Controller verilog file
Verilog-DRAM
- fpga(veriloh hdl)编写的SDRAM程序说明 -fpga(veriloh hdl)SDRAM
LIP2121CORE_pads_dram_controller
- Pads for DRAM CONTROLLER Verilog MODULE
LIP2131CORE_dram_controller
- LIP2131 CORE Verilog DRAM Controller
DRAMsimManual
- DRAM simulator implemented in verilog/VHDL
DDRCHv11
- Source code for ddr2 dram controller for BEEE
5-verilog-programs
- the file contains 5 verilog source codes 1. varying pulses 2. DRAM 3. FIFO 4. UART 5. 16 bit divider
verilog_sdram
- I used code verilog. Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to
sdram controller
- Introduction Synchronous DRAMs have become the memory standard in many designs. They provide substantial advances in DRAM performance. They synchronously burst data at clock speeds presently up to 143MHz. They also provide hidden precharge time and t