搜索资源列表
Compact_Flash_Altera_MAX_II_CPLD
- 基于 MAXII CPLD的对Compact_Flash的读写，擦出操作，内附测试激励文件-MAXII CPLD-based reading and writing of Compact_Flash, sparks operated incentive documents containing test
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- Altera原版MAXII开发板原理图，关于PCI板卡的-Altera development board schematics original MAXII
an489
- 用于MAXII系列EPM240T100 CPLD中UMF使用的例程及说明文档-Routines and documentation for MAXII series CPLD used in UMF
Compact_Flash_Altera_MAX_II_CPLD
- 基于 MAXII CPLD的对Compact_Flash的读写，擦出操作，内附测试激励文件-MAXII CPLD-based reading and writing of Compact_Flash, sparks operated incentive documents containing test
tinycpufiles
- TinyCPU源码,使用Verilog编写的资源占用极少的CPU。Quartus工程，可跑在Altera MAXII CPLD上,也很方便移植到其他FPGA上。CPU使用200个逻辑单元，外设(SPI,LCD等)使用180个逻辑单元。 内含汇编编译器源码(VC2008)，可编译CPU对应的汇编文件。-The sourcecode of TinyCPU, which only consumed very few logical cells, written by Verilog. It is
serial-7seg-display-examples-v100
- Serial 7seg Display maxii