FPGA模拟SPI与MSP430通讯Verilog程序-A verilog program of fpga talks to mcu msp430 using spi

msp430单片机用IO口模拟总线时序，与FPGA进行交互的程序，附源代码，verilog，有简单文档。-msp430 I single-chip analog IO bus with timing, with the FPGA interactive process, with the source code, verilog, a simple document.

开源的MSP430 Verilog源码，供学习使用-Open Source MSP430 Core verilog code, for studying.