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PID
- 用Verilog HDL编写的PID程序代码，成功调试，运行良好。-The source code of PID in Verilog HDL.Simulation was successful.
pid_controler_latest.tar
- PID控制器的verilog实现，做闭环控制器的人可以参考-PID controller verilog implementation of closed-loop controller may make reference to
fuzzy_inference
- VHDL模糊PID控制器模糊推理，推理结果：直接用经验值输出。-Fuzzy PID controller VHDL fuzzy reasoning, reasoning results: the direct use of the experience of the value of output.
pid_vhdl_code
- PID controller... ... ... ... ... ... ... ... ..... -PID controller.....................................................
weifenxianxing
- 微分先行pid，c语言程序，平时做实验用的...大家不用编了，希望对大家有用-Difference to pid, c programming language, usually used to experiment ... we do not have compiled, we want to be useful
fpga_pid
- 基于FPGA的温度模糊自适应PID控制器的设计-FPGA-based PID temperature fuzzy adaptive controller design
232543
- FPGA Implementation of QFT based Controller for a Buck type DC-DC Power Converter and Comparison with Fractional and Integral Order PID Controllers
pid
- It is a verilog code for a vedic multiplier using a barrel shifter
FPGA_PID
- 本文讲的是基于FPGA的模糊PID控制器实现,详细介绍了Verilog HDL怎样用FPGA实现PID控制器-This article tells of fuzzy PID controller based on FPGA implementation details of how to use FPGA Verilog HDL realize the PID controller
DIGITAL-PID
- Use verilog language design DIGITAL-PID source
pidd
- VERILOG HDL pid算法 带仿真验证-pid by verilog HDL
FUZZY
- verilog 模糊PID 通过修改MIF文件 可以完成单个参数整定-FUZZY pid by verilog HDL
fpga
- 利用verilog语言实现fpga双口RAM通信代码，PID算法控制电机速度代码，相关仿真测试程序
fpga
- pid算法控制电机运动，实现fpga与dsp的双口RAM通信(PID algorithm to control motor movement, the realization of FPGA and DSP dual port RAM communication)
pidd
- verilog实现增量式PID算法，实测可用，带modelsim仿真(PID algorithm by verilog)
PI
- PID调节器，非常好用的PID调节器模块(PID regulator, very easy to use PID regulator module)
PID_Verilog
- PID算法用verilog语言实现，实测可用，由三个模块组成(The PID algorithm is implemented in Verilog language. The actual measurement is available. It consists of three modules.)
PID
- 利用Verilog语言实现PID增量式控制，输出占空比(Using Verilog language to realize PID incremental control and output duty cycle)