搜索资源列表
pll
- 用VERILOG语言实现的数字锁相环P-VERILOG language with the digital phase-locked loop PLL
dds
- 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
pll_verilog_code
- 这是一段pll verilog代码，是本人转载！-This is a period of pll verilog code, yes I reprint!
dpll
- 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
PLL
- 可以实现自动锁相环功能的C源程序代码模块，-Can be achieved automatically PLL function C source code modules,
PLL
- verilog PLL的代码，和PLL 的功能介绍，希望能通过，只是简单了点-verilog PLL code, and the function of PLL, the hope, but simply a point
pll_verilog
- verilog model of a P-verilog model of a PLL
pll
- 实现了pll功能，有利于初学者学习pll，采用文本编辑的，利用quartus ii 设计的-Achieved pll function, help beginners learn pll, using a text editor, using quartus ii Design
255
- 全数字锁相环的Verilog源代码，经过仿真调试-All-digital PLL Verilog source code, through the simulation to debug
PLL(pdf)
- 锁相环的设计方法介绍（PLL），可作为设计的参考。-Design method for PLL (PLL), can be used as a reference design.
PLL_50MHz_to_12MHz
- Verilog HDL语言编写EP2C8Q208芯片PLL分频的简单程序，50MHz分频为12MHz-Verilog HDL language，EP2C8Q208 chip， PLL frequency of simple procedures, 50MHz to 12MHz frequency
verilog_PLL
- verilog 写的硬件 pll 锁相环实现-verilog to pll
PLL
- Phase locked loop(PLL) Verilog HDL code
verilog
- 数字锁相环电路verilog源代码 开发环境quartus-Digital PLL circuit verilog source code
PLL
- 该测试程序用过Verilog HDL实现对PLL的分频，既频率管理功能-The Verilog HDL test procedure used to achieve the sub PLL frequency, only the frequency management function
my_uart1_VERILOG_using-PLL
- Verilog uart example, RS232的Verilog例子。PC 发送一个字节（byte）到板子（FPGA），板子回发一个(byte+1).例子简洁，有注释。用到PLL，而且有3：2次数据采用-Verilog uart example，Verilog RS232 example，it s easy to understand, PC send 1 Byte RS232 code to FPGA, FPGA return 1 tht code，but Byte+1， Using P
原边反馈反激变换器开环verilog代码
- 原边反馈反激变换器开环verilog代码(The primary side feedback flyback converter open-loop Verilog code)
FPGA分频
- xilinx spant6 PLL分频，生成4个不同频率的时钟，实现LED闪烁。(xilinx spant6 PLL frequency division)
01_run_led
- verilog软件实现PLL，对系统时钟进行分频(Verilog software implements PLL, frequency division of system clock)
pll
- this is pll for verilog