搜索资源列表
TechXclusives-UsingLeftoverMultipliersandBlockRAM
- Xilinx FPGA using leftover multipliers and block RAM
dma_ram_to_ram
- TMS320F8335 DMA 数据传输 RAM to RAM
spmem.tar
- Sinlge port RAM VHDL/Verilog design
testRAMWR
- 这是一个用VHDL编写的读写双口RAM的程序.-This is a work written in VHDL to read and write dual-port RAM program.
MCU
- MCU控制双口RAM，并与PC机进行数据交换-MCU control of dual-port RAM, and data exchange with PC,
spartan6_fpga_blockram_user_guide
- Spartan6 FPGA中的块存储器使用指南，可以构建为FIFO，ROM，RAM，移位寄存器等。-Spartan6 FPGA block memory in the User Guide, you can build for FIFO, ROM, RAM, shift registers and so on.
ram255x8
- A Basic ram structure with 256 data handling
bram_delay
- Verilog编写的代码，单口RAM用程序控制地址，而不是在仿真文件里面控制地址-Verilog code is written, single-port RAM with the process control address, rather than inside the control address of the simulation file
dpRam1
- Dual port ram design project developed in Xilinx using VHDL
sram
- 单片机写双口RAM，包括读写是否一致的自动检测-Microcontroller to write dual-port RAM, including the automatic detection of the consistency of read and write
dual_RAM
- vhdl语言编写的双口ram及testbench,模块可以在modelsim里进行时序和功能仿真。-vhdl language of the dual-port ram, and testbench, modules, conducted in the modelsim timing and functional simulation.
ram
- 在DSP320F2812中把采集的数据存入RAM中的驱动程序-It provid a interface of saving the data into the ram in the platform of dsp320F2812
RAM.ZIP
- VHDL CODE FOR RAM AND ROM
VHDL
- 双口RAM模块源代码（VHDL）,用于开发FPGA的双口RAM，可以直接下载到工程中使用。-Dual-port RAM module source code (VHDL), for the development of FPGA' s dual-port RAM, can be directly downloaded to the project use.
RAM
- this code is for the ram blocks and it is very essential if you are going to implement asic
FIFO
- 设计了一个具有双时钟信号，双复位信号的FIFO，用于FPGA中的数据缓冲，RAM的定义是参数型，可以根据自己的需求，修改此参数，完成RAM的容量扩展。程序中有详细的说明-Designed a dual-clock signal, double reset signal FIFO, for the FPGA in the data buffer, RAM is defined as parameter type, according to their needs, and modify this
VHDLcodes
- Behavioral descr iption of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.- Behavioral descr iption of ALU, RAM MODULE,
RAM
- 上述文件是一个ram的开发过程。。。次过程的程序都是我自己写的。验证结果正确-The file is a ram in the development process. . . Second process procedures are written in my own. Verification result is correct. . .
DualPort_RAM
- DualPort RAM 中文实验例程。-DualPort RAM Chinese test routines.