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uart2iic
- UART转I2C的Verilog HDL代码，由北京邮电大学《VerilogHDL设计与EDA技术基础》教师编写
UART-VerilogHDL
- 基于verilog语言的uart的实现以及fpga的实现，及供参考-Based on the realization of the verilog language uart and the realization of the fpga, and for reference
uart
- 基于verilogHDL实现的UART收发，带FIFO缓存。-UART transceiver, with a FIFO buffer.
uart_rx
- 硬件描述语言设计的串口UART 接收源代码。-VerilogHDL UART RX RTL SOURCE CODE
UART
- verilogHDL语言实现的uart模块，内部包含波特率生成、uart收、uart发三个子模块，支持配置常规波特率、数据位、结束位和校验位，输入工作时钟125M，时钟不一样时需要修改波特率生成的代码-verilogHDL language of uart module contains an internal baud rate generator, uart receive, uart made three sub-module, configured to support conventi
串口VerilogHDL
- 16倍率采样，带数字滤波，非自己原创，请勿用作商业用途(16 double rate sampling, digital filter, non original, do not use for commercial use)