搜索资源列表
fir
- 用VHDL语言设计有限脉冲响应的FIR滤波器。用户可以在Xilinx ISE环境下运行。-With VHDL language design finite impulse response of FIR filter. Users can run Xilinx ISE environment.
xapp859_rtl
- xilinx PCIE IP核 包括ddr2 memory interface ML555开发板-xilinx PCIE IP cores containing ddr2 memory interface can be used on ML555 development kit
led
- 基于xilinx spartan6 的verilog 代码实现nexys6的流水灯程序-floop leds display on nexys3 xilinx spartan6
all
- 基于FPGA的频率测试器的verilog HDL代码，测试范围1-10MHz，用XILINX公司的ISE软件打开。-Based on FPGA-frequency test the Verilog HDL code, test range 1-10MHz, with XILINX ISE software to open.
AES256-XILINX10.1
- 用XILINX公司提供的NetFPGA板卡并结合软件Xilinx10.1进行系统设计，采用硬件描述语言Verilog实现了 AES-256加密算法。-Provided by XILINX board combined with software Xilinx10.1 NetFPGA system design, using Verilog hardware descr iption language implementation of the AES-256 encryption algorit
MIT_Video-Scaler
- MIT的video scaler论文，文章后面附有c和verilog程序源代码，分为水平缩放和垂直缩放-MIT video scaler papers, articles, source code attached to the back, divided into horizontal scaling and vertical scaling
xapp283
- YUV到RGB的色彩空间转换器(VHDL,Verilog and doc)-Color Space Converter: Y’CrCb to R’G’B’
AD9512_VHDL
- FPGA通过SPI总线控制Analog公司的射频时钟分配芯片的程序，在需要用到高速时钟（GHz）的电路中经常采用，比如数据采集卡及信号回放卡中会经常用到该功能，已经在产品中得到验证，工作稳定。-The VHDL code of controlling AD9512 of Analog Device
ml605_schematics_src_rdf0013_
- xilinx ML605开发板的原理图，包括工程和pdf格式，供电路设计参考，器件为V6 240t-xilinx ML605 schematics V6 240t
DCM
- xilinx SP605开发板的DCM模块验证程序，coreGen工具生成DCM核，由DCM完成时钟分频、倍频、移相等操作-xilinx SP605 development board DCM module validation program, coreGen tool to generate nuclear DCM, completed by the DCM clock divider, frequency, and shift operations equal
yima1
- 本程序是在Xilinx ISE上编写的，它是（7,3）码的另外一种译码方法。里面有源程序和用以仿真的测试文件-This program is written in the Xilinx ISE, it is another (7,3) code decoding method. Source and for the simulation of the test file inside
ml50x_schematics
- xilinx公司的virtex-5开发板原理图 需要的可以下载看一下 希望对你有帮助-xilinx company virtex-5 development board schematics can download look you want to help
freq_counter
- 等精度频率计，用Xilinx FPGA和51单片机实现-Precision frequency meter, etc., using Xilinx FPGA and 51 MCU
61EDA_D408
- 跑表计时器 用xilinx里的各种软件都实现了一遍-Stopwatch timer with Xilinx
ImplementationofFPGAconfiguration
- 基于ARM 微控制器配置FPGA 的实现 摘 要:介绍了基于ARM 内核的ATMEL AT91FR4081 微控制器以J TAG 的ISP 方式配置XILINX XC2S150PQ208 FPGA 的实现过程。这是一种灵活和经济的FPGA 的配置方法。介绍了ISP 和J TAG 的原 理、系统实现的流程、硬件电路设计、J TAG 驱动算法的实现和配置时间的测试结果。-ARM-based microcontroller to configure the FPGA to achieve
aa
- xilinx环境下开发vhdl语言串行接口设计-Xilinx VHDL language development environment serial interface design
Mars-SP3-U_FPGA_manual
- Mars-SP3-U FPGA开发板说明，针对Xilinx的XC3S400，有对原理图的说明和实例操作说明-Mars-SP3-U FPGA development board that Xilinx for the XC3S400, there is schematic diagram of the descr iption and examples of instructions
testbench
- ritting testbench 入门级的还有XILINX的一篇文档how to write a testbench。 你看看这个，看思想。-entry-level ritting testbench are XILINX a document how to write a testbench. You take a look at this, look at the ideological.
manchester_verilog
- Manchester Encoder - Decoder for Xilinx CPLDs Customer Pack-Manchester Encoder- Decoder for Xilinx CPLDs Customer Pack
spartan3e_lab2
- edk9.1关于xilinx大学计划培训的实例程序-Xilinx edk9.1 University plans to provide training on examples of procedures