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file_encryption
- AES分组加密算法做的文件加解密演示, 采用多线程流水线方式对文件进行 读->加密/解密->写 操作.-AES block cipher algorithm for encryption and decryption so the paper presentations, the use of multi-threaded pipelined read on paper-> encryption/decryption-> write operation.
platforms
- A Pipelined Implementation of AES for Altera FPGA platforms.doc
IC-149
- Top-down Implementation of Pipelined AES Cipher
AES
- Pipelined Implementation of AES Encryption Based on FPGA
aes_pipe
- 流水线AES加密VHDL代码，代码规范，值得参考- The VHDL code of Pipelined AES encryption
aes_pipe_latest.tar
- VERILOG IMPLEMENTATION OF PIPELINED AES ALGORITHM
ASE
- 可重构平台下AES算法的流水线性能优化，讲解比较到位，抛砖引玉可以-Reconfigurable platform performance optimization of pipelined AES algorithm, to explain more in place, so you can
AES-pipelined-architecture
- AES算法，采用FPGA实现，重点描述了流水线设计，使用才方法使加解密具有很高的吞吐率-An AES crypto chip using a high-speed parallel pipelined architecture
aes-128_pipelined_encryption_latest.tar
- aes pipelined implementation