AES实现的效率如面积、吞吐量和功耗等，主要是由列混合变换和S 盒的实现决定的。S 盒单元的实现成为设 计的重点，它的硬件实现在很大程度上决定着整个芯片的面积大小。 -AES to achieve efficiency, such as area, throughput and power consumption, mainly by the S box column mixing transformation and the realization of decision. S box

aes descr iption architecture processes vhdl code with pipelining and throughput reduction with an aim to create a faster AES decoding system in FPGA