搜索资源列表
make_interrupt_vector
- altera NIOS软核系统 中断矢量使用例子,基于C语言-altera NIOS soft-core system interrupt vector to use examples, based on the C language
DE2_VGA3
- The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow
ref-sdr-sdram-verilog
- 标准SRD SDRAM控制器参考设计,altera提供 Verilog代码,带有使用手册,大家试试交流一下 -Standard SRD SDRAM controller reference design, altera provide Verilog code, with user manual, we try to exchange some
EPM7032-7128
- altera 公司的EPM7032和EPM7128的DATASHEET-altera s EPM7032 and EPM7128 of DATASHEET
AlteraFPGACPLD1
- Altera FPGA_CPLD设计 基础篇-Altera FPGA_CPLD Part Design
Fifo
- 一个FIFO源代码,基于Altera FPGA-A FIFO source code, based on Altera FPGA
Execise
- altera官方网站上资料的示例代码Quartus II Software Design Series Foundation-altera official website information sample code Quartus II Software Design Series Foundation
FPGA_AD
- 基于Altera的FPGA开发的基于FPGA的AD转换功能,完全通过验证。-Altera s FPGA-based development of FPGA-based AD conversion function, fully validated.
flash_controller
- Altera下的FPGA运行Nios处理器的flash控制器-Altera
altera_maxII_PCI_Verilog
- Altera的MAXIICPLD模拟PCI接口的Verilog代码-Altera
a_block_with_several_functions_with_Verilog_HDL.ra
- Verilog是广泛应用的硬件描述语言,可以用在硬件设计流程的建模、综合和模拟等多个阶段。随着硬件设计规模的不断扩大,应用硬件描述语言进行描述的CPLD结构,成为设计专用集成电路和其他集成电路的主流。通过应用Verilog HDL对多功能电子钟的设计,达到对Verilog HDL的理解,同时对CPLD器件进行简要了解。 本文的研究内容包括: 对Altera公司Flex 10K系列的EPF10K 10简要介绍,Altera公司软件Max+plusⅡ简要介绍和应用Verilog HDL对多功能
ofdm_modulation_v72
- 基于altera 芯片得ofdm调制解调源程序-Altera chips were based on OFDM modulation and demodulation source
HardwareUDP
- Hardware UDP, implementation of UDP based on Altera DE2 using Verilog
Avalon_VGA_Controller
- Vga Controller source code for Altera FPGA
fpga_div
- Altera的FPGA,设计的硬件除法器-Altera' s FPGA, the design of the hardware divider
AlteraSDR-SDRAM
- Altera 官方提供的SDRAM控制器,verilog的-SDRAM controller provided by Altera in Verilog HDL
my_ram_vhdl
- how to infer ram for fpga altera xilinx
PLLTEST
- Altera Quartus to Pll Source
DE2_pin_assignments
- altera DE2开发板的管脚配置文件很好用的哦-altera DE2 development board of the pin configuration files used by Oh well
EP2C5
- Altera FPGA Cyclone II EP2C5 最小系统 开发板-the minimum system of Altera FPGA EP2C5 and or EP2C8