搜索资源列表
cache
- 原创VERILOG HDL 实现CACHE的操作，有需要请下载-original verilog HDL achieve CACHE operation, the need to download
FIFO_8_8
- FIFO先进先出队列，一种缓存、或一种管道、设备、接口（Verilog HDL程序,内附说明）-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
PIPE_LINING_CPU_TEAM_24
- 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,
ping_pong_buffer
- 用寄存器来实现乒乓缓存(Verilog HDL)-Ping-pong with the register to achieve cache (Verilog HDL)
cache
- 缓存器 cache verilog 欢迎下载偶-cache verilog
riscpu
- 一个32位微处理器的verilog实现源代脉,采用5级流水线和cache技术.-a 32 Microprocessor verilog achieve pulse generation sources, used five lines and cache technology.
mipsCPU
- MIPS CPU tested in Icarus Verilog
mips1
- Verilog MIPS design. I found it somewhere on Internet and it is working :-Verilog MIPS design. I found it somewhere on Internet and it is working :))))
5_lined_cpu
- 简单5级流水线CPU的verilog逻辑设计-Simple line 5 of the CPU logic design verilog
dCACHE
- Vhdl写的数据cache,根据Verilog程序改编-Vhdl write data cache
iCACHE
- 用VHDL写的数据cache，基于Verilog版本改编过来-To use VHDL to write the data cache, based on the Verilog version of the adaptation over
PipelineCPU
- 用Verilog实现一个简单的流水线CPU，并运行一个Quicksort程序。这是Berkley，eecs系的计算机系统结构课程实验的实验三。-This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.
icache
- ARM9指令Cache缓存模块的Verilog代码-cache verilog for ARM
code-water-no-cache
- 5级流水无cache的cpu代码，基于verilog，串行，两级流水-cpu code with no water nor cache
verilog-FAQ
- Low power SRAMs have become a critical component of many VLSI chips. This is true for microprocessors, where on-chip cache sizes are growing with each generation to bridge the increasing divergence in the speeds of the processor and main memory. Simu
cache
- 基于MIPS思维方式，verilog语言，简单的cache 控制器设计，状态机共分4个状态，同时内含多样测试文件-MIPS way of thinking, verilog language, simple cache controller state machine is divided into four states, at the same time contains diverse test file
basic-cache
- Verilog codes for cache memory with direct mapping and write back policy.
cache
- 使用Verilog实现对cache命中判断的模拟-Use Verilog to realize the simulation of the cache hit judgment
cache
- verilog 语言写的一个cache 平台是xillix ISE 实现了从cache中取指令命中和缺失情况的处理 -Verilog language to write a cache Platform is ISE xillix The processing of the instruction hit and the missing the cache is realized.
Proj_Cache
- 高速缓存的Verilog HDL实现。（包括直接相联和组相联）-Cache Verilog HDL implementation. (Including directly linked and set associative)