搜索资源列表
setlayout
- cadence 自动增加层和删除层的程序，方便光绘输出-automatic increases in cadence layer layer and delete the procedures for drawing optical output
cale
- 可以在cadence程序中直接调用的calc，方便公英转换-Process can directly call the cadence of the calc, the British public to facilitate the conversion
TMS320DM6467(DaVinciEVM)
- 基于 TMS320DM6467 DaVinci™ 处理器的开发板设计参考资料（光绘、原理图、BOM）. 具有应用手册和原理图. 具有Cadence Allegro SPB的原理图和PCB图. 具有DM6467 入门指南和硬件技术参考. 如:DaVinciHD_EVM_Orcad_RevF.DSN、DaVinciHD_EVM_Layout_RevF.zip、DaVinciHD_EVM_TechRef_RevD.pdf、davincihd_revf_ver6.zip等完整
CadenceVerilogLanguageAndSimulation
- Cadence guide for verilog
cadence_allegro_teach
- 用CADENCE做VHDL语言实验的教程-CADENCE done using VHDL language course experiment
allegro_free_jfskyviewer_15_5
- allegro学习的PDF文档，allegro学习的PDF文档
spHiCreateMultiLabel
- Cadence Virtuso里面创建multiple label的源代码，非常实用-How to Use: 1.Load file "spHiCreateMultiLabel.il" 2.Enter interactive procedure name "spHiCreateMultiLabel()" in CIW. 3.Select correct layer in your LSW. 4.An option form will be displayed. If not ,
ICdesigntools
- IC设计工具很多，其中按市场所占份额排行为Cadence、Mentor Graphics和Synopsys。-IC design tools, many of them ranked by market share for Cadence, Mentor Graphics and Synopsys.
PCICOREGUIDE
- 本指南讲述支持的基于 Virtex™ 和 Spartan™ 架构的 32 位和 64 位核的设计流程，并且介绍 Cadence® IUS v5.8 中的示例设计。-This guide based on the support of the Virtex ™ and Spartan ™ architecture 32-bit and 64-core design process, and Cadence ® IUS v5.8 intr
pcbbook
- pcb射频设计技巧 pcb射频设计技巧 -pcb cadence allegro art pcb cadence allegro artpcb cadence allegro art
cadenceveriloglanguageandsimulationcourse
- cadence verilog lanaguage and simulation course
vlogref
- cadence verilog reference
vani_tut
- A total of 52 files showing examples of shell scr ipting for Cadence NCSIM simulator, multiple single module + testbench examples in verilog 1995/2001, a "Randomized Smoothing Networks" paper (doc)+ppt+verilog codes and test bench from my EE7700 Dist
M54455EVBSCHEMATICS(REV3)
- Mcf54455参考工板原理图Cadence capture格式
skillhelp
- 电子芯片的设计检查语言，在cadence中使用-Electronic chip design checking language to use in the cadence
skill1
- 电子芯片规则检查语言，用于cadence-Electronic chip rule checking language, for the cadence
chlib
- 在cadence virtuoso schematic 自动替换已有的cell到不同的lib-In the cadence virtuoso schematic automatically replace the existing cell to a different lib
CadensePCBSI
- Cadense PCB SI 完整教程文件，可簡單學習PCB SI操作流程-Cadence PCB SI document Lesson1-Lesson6
OrCAD
- OrCAD建立的工程。可用Cadence软件打开。学习用。-OrCAD building project. Cadence software is available to open. Learning to use.
BinKeys
- layout时有西功能没有快捷键，以下脚本就增加一些好用的功能的快捷方式，可更改。-add Cadence virtuoso ShortKey