搜索资源列表
my_design_frequency
- 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号是最重要的信号之一。 下面我们介绍分频器的 VHDL 描述，在源代码中完成对时钟信号 CLK 的 2 分频， 4 分频， 8 分频， 16 分频。 这也是最简单的分频电路，只需要一个计数器即可。-in digital circuits, and often the need for higher frequency for the clock frequency operation, th
clk-div
- VHDL code for a clock divider by 27 circuit with a resulting waveform with 50％ duty cycle..
FPQ.rar
- 分频器的vhdl描述，在源代码中完成对时钟信号CLK的2分频,4分频,8分频,16分频,Divider vhdl descr iption of the source code at the completion of the CLK clock signal frequency of 2 hours, 4 minutes frequency, frequency of 8 hours, 16 minutes frequency
DVF
- 数控分频器的设计数控分频器 端口定义： CLK：时钟输入 D[7..0]：预置数据 Fout：分频输出 说明： D[7..0]作为8位加1计数器的初值，初值越大，分频输出频率越高，反之越低， -NC NC divider divider port the definition of design: CLK: Clock input D [7 .. 0]: preset data Fout: frequency output that: D [7 .. 0] as
frequency
- frequency divider circuit divides the input frequency (clk) by various factors
07070608-2.2
- 利用VHDL语言设计一个分频器，输入为CLK,输出分别为CLK1、CLK8、CLK256、 CLK1024-The use of VHDL language design a divider, input CLK, the output respectively, CLK1, CLK8, CLK256, CLK1024
9600divider
- 任意分频器,可以实现FPGA的CLK分频功能，已通过编译-Arbitrary frequency divider can be achieved FPGA-CLK sub-band capabilities, has passed the compilation
clk_divider
- Simple Clk Divider for FPGA design in Verilog -Simple Clk Divider for FPGA design in Verilog
clk
- 二分之一分频器及其测试程序，是用modelsim仿真实现-One half of the divider and the test procedure is used modelsim Simulation
The-use-of-VHDL-divider-design
- 分频器的各种设计方法， 及源代码，源代码中完成对时钟信号CLK的2分频，4分频，8分频，16分频。-The use of VHDL divider design
clk-fixed-factor
- basic fixed multiplier and divider clock that cannot gate.
clk-imx6q
- The multiplexer and divider of imx6q clock gpu3d_shader get redefined reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl. -The multiplexer and divider of imx6q clock gpu3d_shader get redefined reused as gpu2d_core_sel and gpu2d_core_podf on im
clk-ls1x
- imx integer fixup divider clock for Linux v2.13.6.
clk-divider
- Frontend part of the Linux driver for the Afatech 9005 USB1.1 DVB-T receiver.
clk-corediv
- MVEBU Core divider clock.CORE_CLK_DIV_RATIO_MASK.
clk-frac
- The clock is an adjustable fractional divider with a busy bit to wait when the divider is adjusted.
clk-divider
- linux sound pxa2xx-ac97.c AC97 support for the Intel PXA2xx chip. -linux sound pxa2xx-ac97.c AC97 support for the Intel PXA2xx chip.
clk
- This fixups the register CCM_CSCMR1 write value. The write read divider values of the aclk_podf field of that register have the relationship described by the following table:.
clk-divide5
- 实现5分频计数的veriog电路，简单易懂，欢迎大家下载学习-Achieve 5 divider count veriog circuit, easy to understand, welcome to download the study
vhdl_time
- it is a clk divider