搜索资源列表
nios_ram
- nios 中读写sdram的程序，适用于epc2 cyclone二代FPGA板子-Nios SDRAM read and write the procedures applicable to epc2 cyclone II FPGA board
EP3C25
- Cyclone® III EP3C25的资料-Cyclone 庐 III EP3C25 information
ALTERA
- 5款ALTERA FPGA开发板原理图合集。包括EP1C6Q240C6开发板原理图、Cyclone II EP2C20 原理图。希望对大家有用-5 ALTERA FPGA development board schematic diagram collection. Including EP1C6Q240C6 development board schematics, Cyclone II EP2C20 Schematic. I hope all of you a useful
fpga_sram
- Altera cyclone ep1c6对sram idt71系列的读写时序控制-Altera cyclone ep1c6 of sram idt71 series of read and write timing control
cyclone-2.1.tar
- 超强国际象棋引擎，编码非常规范。便于分析和使用-Super chess engine, very norms coding. Facilitate the analysis and use of
W-cyclone-softp_1.0_src.tar
- 一个ftp搜索引擎的源代码，正在运行中的校内实用的引擎-source code of a on-line ftp search engine
cyc2_cmon_080805
- Verilog 8051 IP Core for Cyclone -Verilog 8051 IP Core for Cyclone II
EP1C6_EP1C12
- Altera FPGA Cyclone I EP1C6 EP1C12 最小系统 开发板 -the minimum system of Altera FPGA EP1C6 and or EP1C12
EP2C5
- Altera FPGA Cyclone II EP2C5 最小系统 开发板-the minimum system of Altera FPGA EP2C5 and or EP2C8
USB1C6
- 基于ALTERA CYCLONE 系列的一个USB实验例程-ALTERA CYCLONE series based on a USB experimental routines
EXPT10_2_TENNIS
- 基于ALTERA CYCLONE 系列的乒乓球游戏实验例程-ALTERA CYCLONE series based on Games Table Tennis experimental routines
Music1
- 基于ALTERA CYCLONE 系列的音乐播放示例实验教程.-ALTERA CYCLONE series based on the music player tutorial sample experiment.
hex2rom_0241_Win32
- This SPI-mode SD Card controller is a free SOPC Builder component that can be used in any SOPC Builder system. The included example design runs on the Nios II Embedded Evaluation Kit, Cyclone III edition (NEEK).-This SPI-mode SD Card controller is a
FPGACycloneIIEP2C5EP2C8pingluji
- 基FPGA Cyclone II_EP2C5 EP2C8的频率计-epga cycklone
cyclone_ii_byteblaster
- cyclone ii EP2C8做的BYTEBLASTER ,电路图,PCB图.完美推荐-cyclone ii EP2C8 do BYTEBLASTER, circuit diagrams, PCB Fig. recommend the perfect
AlteraCycloneIIFPGAStarterBoard
- Altera Cyclone II FPGA Starter Board原理图-Altera Cyclone II FPGA Starter Board Schematic
I2C
- I2C主机端模块 具有avalon-MT总线接口 可挂载在Altera soc系统之上 使NiosII处理器具备I2C通信能力 模块由Verilog HDL编写 并经Cyclone II FPGA测试-I2C master modul which has a avalon-MT interface that can be attached to Altera SOC system. It provides NiosII I2C communication capability . This mo
Cyclone
- 时钟同步主要用在产生10NHZ时钟已近IRIG-B-Clock synchronization
cyclone
- symbian gif动画播放例子-symbian
FFTVHDl
- 基于FPGA的fft实现 摘要：本系统基于Altera Cyclone II 系列FPGA嵌入高性能的嵌入式IP核(Nios)处理器软核，代替传统DSP芯片或高性能单片机，实现了基于FFT的音频信号分析。-FPGA-based realization of the fft Abstract: This system is based on Altera Cyclone II family of embedded high-performance FPGA embedded IP core