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my_ramlib_06
- 包括各种类型存储器的VHDL描述，如FIFO，双口RAM等 -including various types of memory VHDL descr iption, such as FIFO, Dual Port RAM, etc.
dualportRAM
- 双端口RAM的VHDL语言实现。完全在CPLD芯片上测试通过。可以实现对存储器读操作的同时对另外一个空间写操作-dual-port RAM VHDL. Totally CPLD chip test. Memory can be achieved right time to operate while the other was a space operation
can-0.7.1.tar
- PCM9880是一块PC/104界面的双端口隔离CAN总线通讯卡，它提供PC与控制器局域网之间的连接。采用高性能的SJA1000控制器和82C250收发器，每个端口工作的波特率可达1Mbps。内置CAN控制器具有总线仲裁和带错误侦测自动重复传输功能，有效的避免了数据丢失，确保了系统的稳定。端口采用直接存储地址映射，加快CAN控制器访问速度。两个板载控制器对应不同的内存地址，应此两路控制器可以同时独立工作。卡上还有光电隔离器，能保护PC和设备免受接地回路的破坏，大大增强了系统在恶劣环境下的可靠性。
ram
- 一个用VHDL语言编写的双端口存储器程序，可下载在FPGA中使用-Written in VHDL language using a dual-port memory program can be downloaded in the FPGA using
exm9
- 这是在max+plusII环境下编译的双端口存储器模拟实验-This is the max+ PlusII environment of the dual-port memory compiler simulation experiment
dpmem2clk.tar
- Dual port memory VHDL/Verilog design
fpga_memory_rev_1_0
- Various memories for Xilinx and Altera FPGA devices. Single-port and Dual-port versions with various numbers of read and write ports. Bundle also includes read-first and write-first varieties with sync and async clocks. All memory compo
dual
- This module defines a Synchronous Dual Port Random Access Memory.
FIFO
- FIFO,双端口数据存储器，实现数据先入先出的存储器件-FIFO, dual port data memory, data FIFO memory device
DU-RAM
- 本程序是一个双口RAM的读写程序，在很多工程中，特别是存储器中运用广泛-This program is a dual-port RAM read and write procedures, in many projects, especially the extensive use of memory
DPram
- read or write control of dual port memory
netX-DPM-Interface
- This manual describes the user interface respectively the dual-port memory for netX-based products manufactured by Hilscher.
netX500-100_Technical
- This manual describes the user interface respectively the dual-port memory for etX-based products manufactured by Hilscher.-This manual describes the user interface respectively the dual-port memory for etX-based products manufactured by Hilscher.
HilscherDevicetsystem
- System Software DeviceNet • loadable Firmware* • System Configurator SyCon** • OPC Server** • CIF Device Driver • Driver for SoftPLCs** • GSD/EDS files • Documentation for all our Communication Inter
memories-dual-port
- descr iption for memory dual port
SDRAMping-pong-memory-structure
- 双口RAM 的乒乓存储结构（芯片型号CY7C09279） 应用场合为FPGA向双口RAM不断写入数据，PCI总线从RAM读取数据。[已调试验证]-Dual-port RAM, ping-pong memory structure (chip model CY7C09279) applications for the FPGA to the dual-port RAM write data continuously, PCI bus read data from RAM. [Debugging
DPram
- read or write control of dual port memory
DPram
- read or write control of dual port memory
daima
- Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。 模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]位，第三个周期
fffffff
- 如上图所示， Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。 模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]