搜索资源列表
fftmatlab
- fft在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-fft in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
FFT_CORE
- FFT算法的VHDL语言实现 可在Modelsim上运行和调试 -FFT algorithm VHDL in the operation and Modelsim Debugging
modelsim
- 基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft
FFT_64point
- 该工程实现了一个64点DIF FFT，verilog编写，通过Modelsim功能仿真。
FFT288
- 本部分是128点的fft,经过了modelsim的仿真验证.里面采用了华莱士树等结构,整体结构采用2-It is 128 point fft,which has been verificated in the modelsim.In the verilog code ,we use hulaishi tree.we use 288 architecture to complete it.
Quartus_fft_ip_core.rar
- Quartus中fft ip core的使用(modelsim 仿真FFT ip core 结合QUARTUS II 联合调试),Fft ip core in Quartus use (modelsim simulation FFT ip core integration QUARTUS II Joint Commissioning)
FFT
- Verilog实现的FFT模块，供OFDM调制系统使用，可供大家参考学习-Verilog implementation FFT module for the OFDM modulation system used for your reference study
fft_model
- 基二的16点，每点16位FFT计算的modelsim完整工程，可以直接仿真运行-The base 2 of the 16 points, each 16-point FFT calculation modelsim full engineering, simulation can be directly run
64R4SDFpoint_FFT
- 该工程实现了一个64点FFT，verilog编写，采用R4SDF结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point FFT, verilog compiled by R4SDF structure, through the Modelsim functional simulation, compression bag with rtl code, dc scr ipt, the output repo
64pointFFTR2MDC
- 该工程实现了一个64点DIF FFT，verilog编写，采用R2MDC结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point DIF FFT, verilog compiled by R2MDC structure, through the Modelsim functional simulation, compression bag with rtl code, dc scr ipt, the out
32Kfft
- 32KFFT例程，适用于Quartus II 5.0 or later。- This design example requires the following software package: o Quartus II 5.0 or later o FFT MegaCore v2.1.3 o ModelSim version 6.0 or later
FFT_2c8
- 基于FPGA的fft，快速傅立叶变换，带仿真modelsim,硬件测试成功-FPGA-based fft, fast Fourier transform, with simulation modelsim, hardware test is successful
code
- c++语言转verilog语言，程序员不需要学习verilog即可对fpga原型进行快速仿真，本例为catapult c语言的fft程序，可以利用catapult转换工具转成verilog语言， 用modelsim进行仿真，并且可以加各种约束。-c++ program translate verilog program。
fft_streaming
- 关于QuartusII FFT ip核的使用，采用Streaming模式，包含Modelsim仿真程序-About QuartusII FFT ip nuclear use, using Streaming mode, including Modelsim simulation program
fft1024-verilogCODE
- fft 1024点verilog代码,适用于基-4的FFT算法描述，使用quartus，modelsim，-fftpoint 1024 verilog code
FFT64DIF
- 实现64点的快速傅里叶运算，并用modelsim、matlab仿真。(Achieve fast Fourier operations at 64 points, and use Modelsim, matlab simulation.)
exp_fft_test_724
- 在quartus软件中调用FFT的IP核，编辑IP核的驱动模块，使得IP核读入数据进行处理，输出数据。使用modelsim进行联合仿真。(In the quartus software, the IP kernel of FFT is called, and the driver module of the IP kernel is edited, so that the IP kernel is read into the data for processing and output data
fft_32k
- FFT 32K点设计实例v1.0.0自述文件 本自述文件包含以下部分： 工具要求 o Quartus II编译 o ModelSim仿真模型 o MATLAB模型(FFT 32K Point Design Example v1.0.0 README File This readme file for the Fast Fourier Transform (FFT) 32K Point Design contains information about the design exam