搜索资源列表
DE0_NANO_GSensor
- 该代码利用DE0 nano上面的ADI ADXL345三轴重力传感器实现重力感应，根据偏转角度的不同点亮相应方向上面的LED灯，稍加修改，还能够将各个方向上面的重力加速度值实时显示，希望大家喜欢-The code used DE0 nano gravity above the ADI ADXL345 three-axis accelerometer sensors to achieve according to the deflection angle of light in different
de0_Schematic
- Altera FPGA DE0的原理图,包含一些经典的FPGA设计电路及相关的接口-Altera FPGA DE0 schematic, contains some classic FPGA design the interface circuit and related
DE0_TOP
- 这个是DE0的范例代码，对研究FPGA和sopcbuild的人相当有价值！-This is DE0 example code, for research and sopcbuild FPGA great value to people!
DE0_NIOS_SDCARD
- 这个是DE0在niosII环境下驱动SD卡的范例代码，对研究FPGA和sopcbuild和研究SD卡驱动的人相当有价值！ -This is DE0 environment in niosII drive SD card example code, for research and research FPGA and SD card driver sopcbuild great value to people!
DE0_VGA
- 基于fpga的VGA程序代码，已经测试成功-VGA-based fpga code has been tested successfully
DE0_SDCARD
- Altera DE0 FPGA的SD卡读取程序，强力推荐！ -Altera DE0 FPGA SD card reader, highly recommended!
SD
- Altera DE0 FPGA的SD卡读取程序，强力推荐！ -Altera DE0 FPGA SD card reader, highly recommended!
DE0_VGA
- FPGA 的VGA示例程序，基于 DE0开发套件-FPGA Development Kit based on DE0
DE0_Nano_User_Manual_v1.5
- The DE0-Nano board introduces a compact-sized FPGA development platform suited for to a wide range of portable design projects, such as robots and mobile projects.
clk
- 通过Verilog HDL实现多功能数字时钟 开发基于FPGA DE0-Verilog HDL Verilog HDL
7845_VGA
- 此文档是一个DE0的关于VGA的例程，用于FPGA/CPLD开发。-This document is a DE0 VGA routines, to FPGA/CPLD Development .
Altera-FPGA-DE0
- Altera FPGA DE0的原理图 包含一些经典的FPGA设计电路及相关的接口-The Altera FPGA DE0 schematic contains the a classic FPGA design circuits and interface
wireless
- 基于FPGA DE0以及niosII的射频无线发送程序,采用spi接口操作无线模块nrf24l01-To spi interface operation wireless module nrf24l01 of FPGA DE0, as well niosII RF wireless transmitter program
juzhenjianpan
- 矩阵键盘应用于FPGA的verilog代码，使用的是DE0，引脚已分配-Matrix keyboard used in the FPGA verilog code, using DE0, pin has been assigned
signal_generator_430
- 基于430单片机的与DE0 FPGA 的信号发生器，还有测频、测相、测幅、扫频功能。-Based on 430 single and DE0 FPGA signal generators, as well as frequency measurement, the measured phase, the measured amplitude, sweep function.
Phone-Call-Meters-by-Quartus9.2
- 本次设计主要基于FPGA器件完成了一个IC电话计费器的设计，其能够显示用户IC的卡值余额，并能够根据用户当前的话务种类和通话时间进行扣费，并将用户的实时余额和通话时间通过4位LED七段显示器显示出来。整个设计过程采用自顶向下的分块设计方法，即将整个电话计费系统分为电话计费、计时模块和显示模块两大模块，其各模块的实现是基于QuartusⅡ9.2平台使用DE0硬件描述语言编程实现的。-This design is mainly based FPGA devices completed a telep
Line_Tracer_VHDL
- Simple Line Tracer Code Using FPGA DE0 Board
module-DE0
- verilog code for fpga pattern of letters.
DE0-Nano_My_First_Fpga_v1.0
- DE0-Nano My First Fpga
Next186_SoC_DE0Nano_Quartus17.0_23Oct2017
- Next186 x86 for DE0-nano