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FPGA实现模拟I2C协议的过程，包括三个模块，i2c_master_bit_ctrl.v完成位传输功能、i2c_master_byte_ctrl.v完成字节传输功能，i2c_master_top.v完成整个程序的控制功能，并提供给外部程序的接口。 ,I2C Analog FPGA implementation of the Protocol process, including the three modules, i2c_master_bit_ctrl.v achieve bit tran
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I2C总线接口FPGA的实现代码，全部为VHDL语言源码文件，内附设计实用说明文档。-I2C bus interface FPGA implementation of the code, all source files for the VHDL language, included the design and practical documentation.
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《FPGA数字电子系统设计与开发实例导航》的配套光盘，Verilog编写，USB、I2C、MAC的接口设计-"FPGA digital electronic system design and development examples navigation" matching discs, Verilog prepared, USB, I2C, the MAC interface design -err
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FPGA开发板配套VHDL代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。-FPGA development board support VHDL code. Chips for the Mars EP1C6F. Some of the source interface. Including 7 digital tube, I2C communications.
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FPGA开发板配套Verilog代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。-FPGA development board supporting Verilog code. Chips for the Mars EP1C6F. Some of the source interface. Including 7 digital tube, I2C communications.
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FPGA上实现I2C接口.使用方法：
1.拷贝到硬盘，用ISE打开工程文件即可-I2C interface FPGA to achieve
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I2C主机端模块 具有avalon-MT总线接口 可挂载在Altera soc系统之上 使NiosII处理器具备I2C通信能力 模块由Verilog HDL编写 并经Cyclone II FPGA测试-I2C master modul which has a avalon-MT interface that can be attached to Altera SOC system. It provides NiosII I2C communication capability . This mo
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此包为FPGA学习板接口实验程序源代码,共包括13个实验程序,有7段数码管,1602液晶显示,12864液晶显示,I2C总线,串口通信,拨码开关等.-The packet interface to FPGA board experimental procedure to study the source code, a total of 13 experimental procedure, there are 7-segment digital tube, 1602 LCD 12864 LCD,
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ds32c35是dalas生产的实时时钟（RTC）芯片，本程序（在EP2C8Q208C8N上调试通过）在FPGA上构建I2C接口于此时钟芯片通信。可以在LED上动态实时显示时间。利用本程序也可以改编成高精度实时时间测量的程序-ds32c35 is produced by dalas real-time clock (RTC) chip, this program (in the EP2C8Q208C8N debugging via) in the FPGA built this clock ch
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此包中为Mars_EP1C3_S_Core_V2.0 FPGA学习板中的接口实验代码.共包括10个实验源代码:7段数码管,i2c,KEYSCAN,MCU,PS2,UART,VGA，蜂鸣器，跑马灯和拨码开关.
-This learning package for Mars_EP1C3_S_Core_V2.0 FPGA board interface test code. A total of 10 experiments, including source code: 7 segment di
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基于FPGA实现的I2C接口设计，完整的代码，而且有完整的测试代码哦，可用ISE直接打开-FPGA-based implementation of the I2C interface design, complete code, and a complete test code, ISE can directly open,
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用CPLD实现I2C接口，可以移植到FPGA中-Achieved with the CPLD I2C interface can be ported to FPGA,
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用FPGA做的一个I2C接口程序......可以用于I2C通信-FPGA to do with a I2C interface program can be used for I2C communication .... ......
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I2C接口程序，整个工程文件，文人已仿真，下载，在ＦＰＧＡ上测试成功 verilo语言-I2C interface programme,the whole project file,I have simulated and tested in FPGA successfully .verilog language.
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基于fpga的i2c接口模块设计，属于商业版本，利用状态机完成设计-The i2c interface module based fpga designs, a commercial version, using the state machine to complete the design
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用FPGA实现I2C控制器和I2C slave device（类似于I2C接口的EPROM）-FPGA implementation I2C controllers and I2C slave device (similar to I2C interface EPROM)
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Verilig语言描述的I2C Mater控制器的IP核，已经过实践应用，适合于FPGA I2C接口设计应用。本IP核在Altera QII 15.1软件环境下综合，并且包含基于NiosII Gen2处理器的i2c软件驱动代码。-Verilig language I2C Mater described controller IP core, has been the practical application, suitable for FPGA I2C interface design app
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I2C接口FPGA程序,在VIVADO平台实现，已在硬件验证-The I2C interface FPGA program, implementation, the VIVADO platform was validated in the hardware
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基于verilog的i2c接口EEPROM 24lc64的测试程序，包括了eeprom的虚拟模型，实际在硬件上验证没问题，也可以通过modleism进行仿真(Verilog based I2C interface EEPROM 24lc64 testing procedures, including the virtual model of EEPROM, the actual hardware verification is no problem, you can also simulate
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i2c接口的fpga实现，工作在master模式下，verilog(The FPGA implementation of the I2C interface, working in the master mode, verilog)
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