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sha1_verilog
- 安全散列算法的另一种verilog实现，对面积的要求更小，但损失了速度，但在一般系统中，完全可以满足大部分需要了-Secure Hash Algorithm another Verilog realization of the demands of a smaller area, but a loss of speed, but in the general system, fully satisfy the needs of the most
sha_core_latest.tar
- sha1_core_Verilog this is a sha1 function by using Verilog
pancham-0.5
- pancham for MD5 hash function
hash
- 适用于RFID安全认证协议的轻量级hash算法，输出64bit数据。-Applicable to lightweight RFID authentication protocol security hash algorithm, output 64bit data.
MIPS_CPU
- MIPS结构的CPU，采用VHDL编码，附带验证程序，能够跑题hash算法，流水灯，求π程序-MIPS structure of the CPU, using VHDL coding, with the verification process, to get off track and hash algorithms, water lights, find π procedures
md5
- hash algorithm-- md5
JH
- JH算法是第三代安全HASH算法最终入选算法之一，这里是它的完整VHDL实现-JH is one of the the final SHA3 algorithms, this is the whole VHDL implementation of JH.
systemcmd5_latest.tar
- MD5 Hash Algoritm. Source code VHDL
FPGA-Implementation-Of-MD5-Hash-Algorithm
- MD5 Hash Algoritm implementation on a FPGA. Performance evaluation.
HASH-code-implementation-using-VHDL
- implementation for Secure Hash Algorithm 1 SHA-1 in vhdl language contain no test file.