搜索资源列表
uartok
- 采用verilog编写的串口通信程序,采用了状态机设计!程序简单,消耗资源少-Serial communication written by verilog hdl. It is designed with FSM. The program is simple,and consume resource is few.
HDLDumpCmd
- PS2游戏硬盘直灌(HDL)的Windows下VC的源代码,根据HDUMP修改的(改正了几处错误)。命令行方式执行,具体使用说明可在命令行中看到。HDP.exe是执行程序。-PS2 drive straight Irrigation (HDL) VC Windows source code According HDUMP amended (corrected several errors). Command-line approach to the implementation of speci
veriloghdl快速入门
- verilog hdl 快速入门,里面包含很多有用的硬件描述语言的程序-Verilog HDL Quick Start, which contains many useful hardware descr iption language procedures
generic_fifos
- 用HDL语言编写的通用fifo源码,通过对fifo的宽度和深度进行配置,可以产生我们所需要的fifo,还包括fifo的测试程序和仿真Makefile脚本-with HDL prepared by the General fifo source, fifo of the breadth and depth configuration, can produce what we need fifo. also included fifo testing procedures and simulatio
liang_zhu_music_player
- 用Verilog HDL 语言编写的播放梁祝的程序-with Verilog HDL language broadcast of the proceedings Butterfly Lovers
20060412183015974
- 是关于dct的Verilog HDL源代码和测试程序-on the Verilog HDL source code and testing procedures
scu_all_fpga
- 大型嵌入式设备FPGA程序,verilog HDL语言,实现DLL和PCM码流分流。-large embedded FPGA procedures, Verilog HDL, DLL and achieve PCM stream diversion.
systemcTOVerlogHDL
- 一个带波形输出的扫频模板systemC源程序, 该程序在SystemCStudio开发平台下生成, 实现systemC仿真、波形显示以及自动生成Verilog HDL代码。-waveform output with a sweep of the template systemC source, SystemCStudio the program development platform in the next generation, realize systemC simulation,
pro001_buzzer
- 使用FPGA控制蜂鸣器的程序,用Verilog HDL设计,可以是蜂鸣器发出各种不同的声音-FPGA use buzzer control procedures, using Verilog HDL design, it is the buzzer sounded different voices
lcd_controlveriloghdl
- 使用Veriolog hdl 编写手机屏测试程序.-Veriolog hdl prepared to use cell phone screen test.
VerilogHDLPLI
- Verilog HDL的PLI子程序接口,用于与用户C程序在2个方向上传输数据,可用xilinx ISE,quartusii或modelsim仿真,-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii or modelsim simulation,
FPGA_test_frequency
- 本原码是基于Verilog HDL语言的FPGA原程序,主要用于测频率,特点主要是可以更快地测频。实时性更高。-primitive code is based on Verilog HDL FPGA original program, mainly for the measurement frequency, the main features can be faster frequency measurement. Real-time higher.
led_decode
- 用veilog HDL编的七段译码显示电路。自己做的第一个此类程序,编译仿真通过,感觉不错-veilog HDL series with paragraph 107 of the decoder show circuit. I have done the first such procedure, compile through simulation, feeling good
count_usebasketball
- 一个小程序,用Veilog HDL编写的,可以用于篮球比赛的倒计时牌,已在max-plusII上仿真通过。-a small program, prepared by the Veilog HDL, can be used for the basketball game countdown. have max-plusII on through simulation.
fir_finall
- 用verilog编写的fir滤波器程序,开发环境可以用ise quartus或active hdl等-verilog prepared with the fir filter process development environment can be used ise quartus or other active hdl
Verilog的135个经典设计实例
- Verilog的135个经典设计实例,部分摘录如下:【例 9.23】可变模加法/减法计数器【例 11.7】自动售饮料机【例 11.6】“梁祝”乐曲演奏电路【例 11.5】交通灯控制器【例 11.2】4 位数字频率计控制模块【例 11.1】数字跑表【例 9.26】256×16 RAM 块【例 9.27】4 位串并转换器【例 11.8】多功能数字钟【例 11.9】电话计费器程序【例 12.13】CRC 编码【例 12.12】(7,4)循环码纠错译码器【例 12.10】(7,4)线性分组码译码器【例
Verilog HDL
- 2015年全国电子设计大赛F题,时间间隔测量模块,占空比测量模块,ISE编写的verilog程序。(2015 national electronic design competition F title, time interval measurement module, verilog program written by ISE.)
uart
- 电脑端发送数据与FPGA接收数据程序,uart模块,以及一部分项目里包含的其他的程序(Program for sending data from computer and receiving data by FPGA, UART module)
test_ADC
- verilog 数模转换程序,包括AD与DA,AD能够对于波形的数值进行输出,使用的是ego1开发板(transition of A/D signal)