搜索资源列表
i2c.tar
- 是个I2C软核，使用verilog和vhdl实现的，含有testbench。-this is soft core of I2C in verilog rtl and VHDL.
i2c
- i2c rtl code , document, simulation
i2c_master_slave_latest[1].tar
- I2C Core VHDL RTL Source Code for Synthesis
i2c
- I2C verilog代码，支持master和slave方式，内置CPU接口-I2C verilog RTL code， support master and slave mode
i2c
- I2C的RTL源码，verilog，验证过的-I2C verilog RTL
I2C_Verilog_Model
- 该源程序包是I2C的Verilog语言模型，包括以下4个部分：RTL源代码，测试平台，软件仿真代码，说明文件。-This source package is I2C bus model based on Verilog language. It has the following 4 parts: RTL code, testbench, sofeware simulating code, help document.
i2c_testbench
- i2c verilog rtl with testbench very good code and works perfectly with cadence ius and ncverilog
i2c_master
- verilog i2c master rtl+testbench 转自特权同学(verilog i2c master rtl+testbench)
i2c_slave
- Verilog i2c slave rtl + testbench 仿真ok(Verilog i2c slave rtl + testbench)