搜索资源列表
SmartFusion_Libero
- libero环境下的ADC采样的硬件驱动设计-libero environment ADC sampling hardware-driven design
APB3_slave_libero
- libero环境下实现的smartfusion开发板的arm和FPGA通信的硬件设计-libero environment SmartFusion development board ARM and FPGA hardware design of the communication
CS5361_DAT
- CS5361 ADC 驱动程序,其中还有时钟部分,这里是数据采集部分. 使用VerilogHDL编写,在Libero中编译,使用Actel芯片测试通过.-CS5361 ADC drivers, of which there are clock parts, here is the data collection using VerilogHDL written, compiled in Libero using Actel chip test.
DisplayingPOTLevelwithLEDs
- SmartFusion A2F200M3G DisplayingPOTLevelwithLEDs-Under the IDE of Libero,using smartfusion A2F200M3G,to realize the control of Leds
Integrator
- libero环境下利用verilogHDL实现积分器功能-libero environment using an integrating function verilogHDL
Differentiators
- libero环境下利用verilogHDL实现微分器功能-libero environment using verilogHDL achieve differentiator function
I2C_Single_Master
- I2C Single master written in Verilog Libero Designer core generator.-I2C Single master written in Verilog Libero Designer core generator.
reed_solomon_decoder
- Reed Solomon Decoder written in Verilog Libero core generator.-Reed Solomon Decoder written in Verilog Libero core generator.
UART
- General purpose UART written in Verilog Libero core generator.-General purpose UART written in Verilog Libero core generator.
RX_ASYNC_for_module_UART
- Rx Async for module UART written in Verilog Libero Designer core generator.-Rx Async for module UART written in Verilog Libero Designer core generator.
TX_ASYNC_for_module_UART
- Tx Async fpr module UART written in Verilog Libero core generator.-Tx Async fpr module UART written in Verilog Libero core generator.
HTML
- 国外商用时尚网站HTML 简绍产品用 Nam libero tempore, optio cumque nihil impedit quo minus id quod maxime placeat facere possimus, cum soluta nobis est eligendi optio cumque nihil impedit quo minus id quod maxime placeat facere possimus, omnis voluptas assumenda
microsemi
- microsemi的Libero IDE 软件内部IP核详解(Microsemi's Libero IDE software internal IP kernel details)
fiddler-linux
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tincidunt
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Castalia-3.2_OMNeT-IDE_Windows_Linux-master
- rutrique libero auctor. Nam mattis diam lorem, vel pretium magna scelerisque suscipit. Aenean ultrices, quam sed volutpat eleifeauris augue lacinia lorem, at pharetra erat tortor at arcu. Vestibululesuada dui finibus semper sodales. Curabitur ss, fel
mixim_2.3-inet_2.1-bundle.tar
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IDS_v9
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