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NAND256R3A_VE1
- 256Mbits (x8) 528 Bytes Page, NAND Flash Memory Verilog HDL Model User Manual -256Mbits (x8) 528 Bytes Page, NAND Flash Memory Verilog HDL Model User Manual
rom
- Read-only memory,Verilog code
Samsung 8G x 8 Bit NAND Flash Memory SPEC & Simulatiom model
- Samsung 8G x 8 Bit NAND Flash Memory SPEC and verilog Simulatiom model
iic 用verilog语言写的FPGA iic驱动程序
- 用verilog语言写的FPGA iic驱动程序，实现对存储器的读写，有需要的可以下载看看哦！-Language used to write verilog FPGA iic driver to achieve the memory read and write, there is a need can be downloaded to see Oh!
Chapter10
- 第十章的代码。 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相
fifolifo
- fifo filo verilog 程序！先入先出数据存储器的程序和先入后出程序！-fifo filo verilog program! First in first out data memory of the program!
Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
flash
- fpga的FLASH读写VERILOG代码。希望对大家有用-the verilog code of fpga read/write flash
rom
- 基于verilog的rom存储器 简单实用 初学者的好材料-Rom memory, based on simple and practical verilog' s good material for beginners
M25P32_VG_12_50MHZ
- Serail Nor Flash Memory Model
fifo
- 先入先出缓冲存储器，采用verilog hdl-FIFO buffer memory, using verilog hdl
cam_test
- 一个验证过的CAM源码（CAM=Content Address Memory）。语言为verilog-CAM a verified source (CAM = Content Address Memory). Language for Verilog
memory
- Verilog写的内存控制器代码. 很好,很容易看懂-Verilog code to write the memory controller
RAM_Examples
- Verilog hdl code for representing ram and rom "memory" using many methods
Memory
- Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
RT_8051_memory
- 8051 RT Memory Verilog-8051 Memory
dpmem2clk.tar
- Dual port memory VHDL/Verilog design
MEMORY_CONTROLLER_ASSIGNMENT
- memory controller design in verilog
Verilog秒表设计
- 用verilog在basys2开发板上实现一个具有置零、开始、暂停、记忆功能的秒表。(Implement a stopwatch which containing reset,pause,start,memory functions with the verilog on the vivado based on the basys2 development board.)
memory生成和接口说明
- memory生成结构说明文档；使用Verilog语言(Memory generated structure descr iption document)