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Gpio_i2c
- 基于RMI1250(MIPS 32内核)通过GPIO模拟IIC驱动源码,在WinCE 5.0下测试通过
Serial
- 基于WinCE 5.0 下的MIPS 32 内核的Au1200(AMD)的UART驱动,支持数据流控,经车载平台测试性能稳定,传输数据率高
MIPS32_Instruction_Set_Quick_Reference
- MIPS 32 处理器 汇编指令 速查手册
MIPS32ALU
- VHDL MIPS 32位ALU的设计,基于Quaryus II平台-VHDL MIPS 32 位 ALU design platform based on Quaryus II
MIPS32Barrelshifter
- VHDL MIPS 32位桶形移位器的设计-VHDL MIPS 32-bit barrel shifter design
CPU
- 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
mipscpudesign
- cpu设计实例mips。MIPSI指令集32位CPU(1)MiniCore设计实例全32位操作,32个32位通用寄存器,所有指令和地址全为32位 (2)静态流水线(3~5级) (3)Forwarding技术 (4)片内L1 Cache,指令、数据各4KByte,硬件初始化 (5)没有TLB,但系统控制协处理器(CP0)具有除页面映射外的全部功能 -cpu design example mips. MIPSI instruction set 32-bit CPU (1)
MIPS-Implementation
- mips 32 implementation
cpu
- 基于MIPS指令集的32位CPU设计与VHDL实现-Based on the MIPS instruction set of the 32-bit CPU design and the realization of VHDL
singlecycleMIPS-lite
- mips processor——32bit-mips processor- 32bit
CPUsourcecode
- 本设计实现了一个具有标准的32位5级流水线架构的MIPS指令兼容CPU系统。具备常用的五十余条指令,解决了大部分数据相关,结构相关,乘除法的流水化处理等问题,并实现了可屏蔽的中断网络。-This design implements a standard 32-bit 5-stage pipeline architecture of MIPS instruction compatible CPU system. Instructions with more than 50 commonly use
PipelineCPU
- Quartus II 7.2环境中,采用硬件描述语言VHDL独立完成了基于MIPS指令集的32位RISC处理器的逻辑设计-quartusII mips pipeline 32bit cpu design
MIPS
- 32位MIPS系列的系统,实现加减乘除与或非等等基本功能-32-bit MIPS family of systems, or non-realization of Math and basic functions, etc.
32mips-cpu
- 基于32为MIPS指令设计的cpu,32 for the MIPS instruction based on the design of the cpu-32 for the MIPS instruction based on the design of the cpu
32registergroup
- VHDL MIPS 32位寄存器组的设计-VHDL MIPS 32-bit register set design
lesson6_pipelining
- Analysis of the MIPS 32-bit, pipelined processor using synthesized VHDL
Multiplier-shifter-design-tradeoffs-in-a-32-bit-m
- excellent paper which is about the design of MIPS Architecture in the field of computer science and technology
mips--cpu
- 本文基于32位 MIPS CPU的体系架构,采用Xilinx ISE 9.1i软件,通过使用Verilog语言编写了32位MIPS单周期和多周期CPU的程序,完成了其逻辑设计并进行了仿真测试。-Based on a 32 MIPS CPU architectures using the Xilinx ISE 9.1i software, write a 32-MIPS, single cycle and multi-cycle CPU program completed its logic de
montadormips
- implementation of assembly program for MIPS 32 bits, the program was developed in portuguese