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IIRtest
- quartusII9.0开发环境下巴特沃斯IIR滤波器的实现完整的工程文件，同时里面有文档详细说明如何用modelsim对altera芯片进行仿真-development environment quartusII9.0 Butterworth IIR filter to achieve a complete project file, but there are documents in detail how to use modelsim to altera-chip simulation
QuartusII9.0crack
- quartus 2 v.9.0 program
quartusii9.1_handbook
- quartusii9.1_handbook用户手册吗，是最新版的altera fpga开发软件资料，altera官方资料，是学习altera fpga的必备资料，（全英文版）中文版我会尽快上传-quartusii9.1_handbook user manual you, is the latest version of the altera fpga software development information, altera official information is essentia
zhuangtaiji
- 检测姓名序列的状态机。使用VERILOG编写。平台是QuartusII9.1。Cyclone -Detection of sequence state machine name. Prepared using VERILOG. Platform is QuartusII9.1. Cyclone III
Crack_Altera_6.0-9.1
- DSP builder6.0-9.0和quartus ii6.0-9.0等版本的破解器，注意运行破解器时最好关闭杀毒软件，否则有可能会出错-DSP builder6.0-9.0 and quartus ii6.0-9.0 and other versions of the cracker, pay attention to when the best off running the cracker antivirus software, or they may be wrong
exp_micro_s
- 自己在QuartusII9.1及Modelsim新版本中完成的microsequencer实例的工程文件。 1.echo uart,接收rx_data,再回复！ 2.运行时请注意完整路径： D:\EXP\EXP_SOPCbuilder\exp_micro_s 3.UART数据输入问题？ 3.1 MODELSIM中w完信号后，run/restart一次。 3.2 设置clock=20ns。 3.3 命令行中输入uart_drive调出uart_
uart_top
- 串口驱动程序，quartusII9.1开发。-Serial port driver, quartusII9.1 development.
QuartusII9.0crack.RAR
- QuartusII9.0破解补丁，破解教程-QuartusII9.0 crack patch
NCO_Test
- 代码是对通信中的NCO模块的仿真，基于QUARTUSII9.0软件，代码编译成功，并且功能仿真已经实现-Code NCO module communication the simulation, based QUARTUSII9.0 software, code compiled successfully, and the functional simulation has been achieved
fir
- 基于FPGA的低通滤波器的设计，仿真环境是QuartusII9.0。对信号进行低通滤波，编程成功。希望对大家有所帮助-FPGA-based low-pass filter design, the simulation environment QuartusII9.0. The signal is low-pass filtering, the programming was successful. We hope to help
dualpolling
- 两级轮询系统的FPGA实现，QuartusII9.0环境，VHDL语言，已编译仿真通过和指定管脚，可直接下载至板，不同板请重新制定-Two polling system FPGA, QuartusII9.0 environment, VHDL language, compiled through simulation and the specified pin can be directly downloaded to the board, please re-enact different b
mux16
- 十六位乘法器的verilog hdl 实现 及 modelsim 仿真 环境为quartusii9.0 自动调用modelsim 6.5输出仿真结果-fpga verilog hdl modelsim quartusii 16-bit multiplier
bahe
- 采用verilog设计的拔河比赛，在QuartusII9。0仿真验证并在DE2上测试过-Using Verilog to design the tug of war, in QuartusII9. 0 simulation and test on DE2
RS
- RS(255,239)和(2,1,7)卷积码的级联码的quartusii9.0上实现了的，保证能用-RS（255,239）and (2,1,7).it has been verified in quartusii9.0.