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内存映射
- 内存映谢范例 内存映谢范例 内存映谢范例-RAM memory model Xie Ying Ying Ying Xie Xie memory paradigm example of memory model Xie Ying
uart1
- 使用DSP软件实现UART功能.一般教科书上提供的UART收发的程序往往是一段采用轮循（Polling）方式完成收发的简单代码。但对于高速的AVR来讲，采用这种方式大大降低了 MUC的效率。在使用AVR时，应根据芯片本身的特点（片内大容量数据存储器RAM，更适合采用高级语言编写系统程序），编写高效可靠的UART收发接口（低层）程序。下面是一个典型的USART的接口程序。-use DSP software UART functions. General textbooks UART transce
FRAM1808_256
- FM1808是一种掉电可保存的RAM存储器,应用很广泛.-FM1808 is a power-off kept in RAM memory, which is widely used.
VHDLRAM
- 介绍vhdl硬件描述语言的特点及设计思想，运用vhdl硬件描述语言实现计算机原理实验中RAM存储器的设计方法，重点描述了对传统计算机组成原理实验中移植到基于CPLD平台的思想-introduced vhdl hardware descr iption language features and design ideas, vhdl use hardware descr iption language computer science experiments RAM memory design,
MYCNetControl
- 图形显示CPU内存利用率 图形显示CPU内存利用率-graphics CPU utilization of graphics RAM memory CPU utilization
flash_fs
- FLASH文件系统的源码，Flash memory is a nonvolatile memory, which allows the user to electrically program (write) and erase information. The exponential growth of flash memory has made this technology an indispensable part of hundreds of millions of
ram
- RAM， Random-access memory，Verilog code
ram
- 一个用VHDL语言编写的双端口存储器程序，可下载在FPGA中使用-Written in VHDL language using a dual-port memory program can be downloaded in the FPGA using
8051 Memory Write Example Program
- 8051单片机的存储器操作源程序，通过调用这个程序可以实现对存储器的控制-8051 memory operation source, by calling this procedure can be achieved for the memory control
ram
- 存储器模块生成，采用16位数据总线，5位读写地址总线，异步清零！-Memory modules generated, using 16-bit data bus, 5 to read and write address bus, asynchronous Clear!
Dtmdesign
- 利用8051单片机、常用数字逻辑接口器件、ROM、RAM存储器器件、单总线数字温度传感器DS18B20，设计一种基于单片机的数字温度计，温度检测范围为0-90度，要求能够通过键盘设定温度超限报警值，通过LED或LCD显示当前温度值。-The use of 8051, commonly used digital logic interface device, ROM, RAM memory devices, single-bus digital temperature sensor DS18B20
RAM
- 曾经做过一电子竞赛课题部分，硬件描述语言VHDL做数据存储器512位存储深度，-Competition has been a subject of electronic parts, hardware descr iption language VHDL do data memory storage depth of 512,
ram
- 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个RAM存储器。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware descr iption language to achieve a RAM memory.
rom_prf_gen
- 用ram存储顺序，用此方法也可以实现其他的顺序数据，代码用verilog编写-Ram memory with the order can be achieved using this method also the order of the other data, write code using verilog
RAM
- 调试运行程序RAM.ASM。对62256进行读写。若L1灯闪动，表示62256RAM读写正常。一直亮说明扩展数据存储器有损坏-Commissioning program RAM.ASM. Read and write to the 62256. If L1 lights flashing, that 62256RAM read normal. Light that has been extended data memory is damaged
android-cpu-net-ram
- android开发内存，cpu等信息读取-android development of memory, cpu and other information to read
ram
- 此代码可以是FPGA内部ram存储器在读取一系列数据后，然后每间隔1秒钟读出来。-This code can be read in the FPGA internal ram memory after a series of data, and then read out at intervals of 1 second.
RAM++
- 单片机内部 RAM自加，并可通过memory监控(The internal RAM of the single chip microcomputer is added, and can be monitored by memory)
SAMSUNG_e6=PC2-5300
- Memory and Storage SAMSUNG_e6=PC2-5300
RAM
- F5XX RAM 存储器根据RAM空间的不同，分为多个Section 每个Section 4k 拥有四种模式。每个Section 关闭可以由RCCTL0 来控制，一旦某个section 被关闭后那么以前存储的数据都将丢失，对已经关闭的SECTION 进行写是没有效果的，被关闭RAM SECTION 部分读为0；(F5XX RAM memory is divided into several Section, each Secti