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时序逻辑：VHDL实例---移位寄存器
- 时序逻辑种类：VHDL实例---移位寄存器-sequential logic types : VHDL examples --- Shift Register
vhdl.rar
- 74ls164 8位移位寄存器 串入并出,74ls164 8-bit shift register and a string into
multiplier-accumulator(vhdl)
- 用VHDL语言描述和实现乘法累加器设计,4位的被乘数X和4位的乘数Y输入后，暂存在寄存器4位的寄存器A和B中，寄存器A和B的输出首先相乘，得到8位乘积，该乘积再与8位寄存器C的输出相加，相加结果保存在寄存器C中。寄存器C的输出也是系统输出Z。(原创，里面有乘法部分和累加部分可以单独提出来，很好用) -With the VHDL language to describe the design and realization of multiplier-accumulator, four of
24_bit_register
- 自己使用VHDL语言编写的24位寄存器.主要用于DDS中-24bit_register
ShiftRegister
- Shift register verilog code
project
- synthesizable code for shift register of user defined size
shiftregister
- Shift Register. VHDL code and its testbench.
UniversalRegister
- 普通的缓冲器 这种设计是一个普通的缓冲器，可以做一个直接的缓冲器，也可以做一个双向的转移缓冲器，还可以做一个递增的计数器和递减计数器-Universal Register This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter.
register
- it is source code of 32 bit register and testbench for tht register written in verilog.
mux_reg
- VHDL code for a multiplexer and a parallel/serial in parallel/serial out shift register
shift_register
- shift register it is shifte register for vhdl coding
register
- 计算机组成原理实验通用寄存器组。仅供大家参考。-Computer Organization experimental general-purpose register group. Only for your reference.
vhdl-pdelay
- programmable delay register (16-bit) in VHDL source code
VHDL
- 时钟发生器用于生成不同的时钟信号clock、clk2、fetch与alu_clk，产生的时钟信号clk送往寄存器与状态控制器，时钟信号clk2送往数据控制器与状态控制器，信号fetch送往数据控制器与地址多路器，信号alu_clk送往算术逻辑单元。-Clock generator to generate different clock signals clock, clk2, fetch and alu_clk, generated clock signal sent to register w
sr12univ_a
- universal shift register vhdl
shift16
- The data in the shift register in shift pulses can move or by bit right next moves left, data can be parallel input, parallel output, also can serial input, serial output, still can parallel input, output, serial input, serial, parallel output is fle
load--clr-register
- 带load、clr等功能的寄存器 VHDL语言编写，亲自运行，成功-Register VHDL language, with features such as load, clr personally run
16x4-register-VHDL
- 16x4的寄存器的VHDL硬件描述语言的实现，可以用quaturs实现。-16x4 register based on VHDL
shift-register-VHDL
- 移位寄存器的VHDL实现，可以用quaturs实现。-shift register based on VHDL
Register
- this code is by VHDL language for register ent counter register and