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RISC模型机
- 设计一台RISC模型机，要求具有以下功能：输入包含10个整数（无符号数）的数组M，按从小到大的顺序输出这10个数。
cpudesign_doc.rar
- RISC cpu设计的经典教程，牛人讲义哦。,RISC cpu classic design tutorials, cattle were handouts Oh.
8bitRISCCPU
- 8bit RISC cpu 设计资料 包含夏宇闻老师的教程第8章-8bit RISC cpu design
RiscCpu
- Verilog-RISC CPU 代码 实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。 北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware descr iption language, and design methods. The procedure adopted
ALU
- vhdl代码 使用quartus编译 cpu中 alu的设计 可作为课程设计的参考 此为16的运算器-VHDL code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
OR1200_verilog
- or1200开源risc cpu的verilog描述实现，cpu源代码分析与芯片设计一书的源码-or1200 open source Verilog descr iption of the risc cpu realize, cpu source code analysis and chip design source book
risc
- 嵌入式risc处理器源码，包含设计文档，原理图，testbench，及外围接口，使用verilog实现。-Source embedded RISC processors, including design documents, schematics, testbench, and peripheral interfaces, the use of Verilog to achieve.
32bit_RISC_CPU
- 32 risc cpu的参考设计，内涵完整的testbench-32 risc cpu s reference design, the connotation of complete Testbench
dkljfkjls
- RISC处理器设计.ppt RISC处理器设计.ppt RISC处理器设计.ppt-RISC processor design. PptRISC processor design. PptRISC processor design. PptRISC processor design. PptRISC processor design. Ppt
computer2
- 一款8位RISC MCU的设计-An 8-bit RISC MCU Design .........
computer12
- 基于FPGA的八位RISC CPU的设计-FPGA-based RISC CPU design eight ....
risc32
- VHDL设计实例与仿真中的32位risc代码，经仿真确定可以通过-VHDL design and simulation of the 32-bit risc code, as determined by simulation
32RISC
- 32位risc设计过程步骤讲解，非常专业，希望对大家有帮助！-32 steps to explain the design process risc, very professional, we want to help!
cpudesign
- Risc 32位CPU设计方法，由牛人主讲，可以好好学习-Risc 32 Wei CPU design methodology, from the cattle were speakers, you can learn
RISC-DSP
- RISC-DSP组合处理器设计优化[1].-RISC-DSP processor design portfolio optimization [1].
RISCCPU
- 简单的CPU设计流程PPT，用于教学目的，可综合的verilog HDL设计。-A simple CPU design process PPT, for teaching purposes, can be integrated verilog HDL design.
risc1200
- risc cpu设计源码，全部资料 欢迎下载-risc cpu core
RISC_SPM
- 简单risc cpu设计，本人通过书中的代码，又加了一些，已通过仿真。-Risc cpu simple design, I code by the book, but also added some, has been through simulation.
zxcpu
- 用VHDL语言设计了一个含10条指令的RISC处理器。假定主存可以在一个始终周期内完成依次读写操作且和CPU同步，系统使用一个主存单元。处理器指令字长16位，包含8个通用寄存器，1个16位的指令寄存器和一个16位的程序记数器。处理器的地址总线宽度16位。数据总线宽度16位，取指和数据访问均在一跳蝻数据总线。处理器支持包含LDA，STA，MOV，MVI，ADD，SUB，AND，OR，JZ，JMP十条指令。其中仅有LDA和STA是访存指令。-VHDL language design with a R
A-RISC-Design
- RISC设计：MIPS指令集控制器核，详细介绍一款32位risc-cpu。-A RISC Design:Synthesis of the MIPS Processor Core