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aes_verilog
- A RTL verilog coding for the project AES, which is a cryptography based concepts
Altera-Recommended-HDL-Coding-Style
- Altera 推荐的HDL编码风格，在学习HDL的时候比较重要，另外对HDL到RTL的映射有一定的帮助。-Altera Recommended HDL Coding Style
rtl
- LCD1602 Verilog 代码实现。包括数据读写，地址读写，初始化。支持4位总线格式。注意:此程序已经在ML506板子上验证过。本人花了好几天调试，开发出来的。值得推荐。-Verilog coding for LCD1602 display
coding-style
- QA培训资料,一、 RTL CODE 规范-QA training materials, a, RTL CODE specification
aFifo.vhd.txt
- Async. FIFO for rtl coding and simulation
verilog-coding-rules
- Verilog HDL可综合RTL级代码设计规范及风格-Verilog HDL RTL level code design specifications and style
interleave
- 使用xilinx13.1编译通过的块交织编码，能够生成RTL图和technology schemtic图-Block using the xilinx13.1 compiled through intertwined coding can generate RTL diagram, and technology schemtic of Figure
RTL-coding-guidelines
- RTL coding guidelines Offer a collection of coding rules and guidelines. Make HDL Codes readable, modifiable, and reusable. Achieve optimal results in synthesis and simulation.
pipe_mul
- 移位加乘法器的实现；移位加乘法器的流水线结构的实现。代码清晰明了。-multiply verilog RTL；pipelin multiply verilog RTL；good coding stytle