搜索资源列表
DDR-SDRAM_IP_core
- DDR-SDRAM接口模块verilog源代码,可用作IP核使用,已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven
Linux_bc
- 对vga接口做了详细的介绍,并且有一 ·三段式Verilog的IDE程序,但只有DMA ·电子密码锁,基于fpga实现,密码正 ·IIR、FIR、FFT各模块程序设计例程, ·基于逻辑工具的以太网开发,基于逻 ·自己写的一个测温元件(ds18b20)的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example(McGr ·这是CAN总线控制器的IP核,源码是由 ·FPGA设计的SDRAM控制器,有仿真代码 ·xili
sdram_vhd_134
- This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is Verilog. This code is based Xilinx FPGA Playform.
SDR_SDRAM_IP
- SDR SDRAM 控制器,Altera官网重要资料。内涵说明文档,和VHDL与Verilog两种设计IP。-SDR SDRAM controller from Altera
Altera-SDRAM_controller-IP-CORE
- ALTRA官方提供的SDRAM的控制内核,VHDL和VERILOG版本都有,希望对大家有用-The ALTRA official SDRAM control kernel, VHDL and VERILOG version have the hope that useful
sdr-sdram-verilog
- SDRAM IP CORE,ALTERA提供-SDRAM IP CORE,ALTERA
61EDA_C915
- altera公司的SDRAM 控制器的ip core源代码 里面包含verilog及vhdl两种语言编写的 方便选择-altera company SDRAM controller ip core source code which contains verilog and vhdl two kinds of language for easy selection
sdr_sdram
- sdram使用接口仿真,altera公司ip使用方法(sdram verilog. SDRAM using interface simulation, Altera company IP use method)