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DDRSDRAMcontroller
- DDRⅡ+SDRAM控制器设计实现相关学问论文,希望对基于FPGA实现SDRAM控制的有所帮助-DDRⅡ+SDRAM controller.rar
burstpage
- SDRAM控制器在FPGA实现源代码,能实现burst传输-SDRAM controller in FPGA realization of the source code, can achieve burst transfer
AMBA
- 基于AMBA总线的DDR2 SDRAM控制器研究与实现-AMBA bus-based Research and Implementation of DDR2 SDRAM Controller
control_interface
- sdram控制器i/o接口模块的VHDL源程序文件,可直接用-sdram interface
Sdram_Control_2Port
- 双端口SDRAM控制器,将SDRAM虚拟成两个端口,已经在ALTER DE2开发板的硬件上验证通过,采用Verilog HDL语言编写。-Dual-port SDRAM controller, SDRAM virtual into two ports, have ALTER DE2 development board hardware verification by using the Verilog HDL language.
sdram_controller
- SDRAM 控制器的 verilog 源代码, 针对Micron 的SDRAMS设计,支持全部的指令, 已经经过逻辑验证,并实际用在芯片设计中,作为一个模块,正常工作.-SDRAM controller verilog source code, for Micron' s SDRAMS designed to support all of the instructions, the logic has been verified, and actually used in chip des
DDR2deFPGAsheji
- 使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器以及DDR2 SDRAM操作时序-Using the Virtex-4 FPGA devices to achieve DDR SDRAM and DDR2 SDRAM controller operation timing
sdram_ctrl
- sdram 控制器 含testbench-sdram controller with testbench
SDRAMcontroler
- SDRAM控制器,Verilog代码以及相关文档-SDRAM controller, Verilog code, and related documentation
ddr
- DDR SDRAM 控制器 VHDL代码,可支持32bits数据总线-VHDL code for DDR SDRAM controller, supporting 32bits data bus
sdr_sdram
- sdram控制器,verilog语言写的-sdram controller, verilog language to write
1-SDRAM
- 基于FPGA的SDRAM控制器的设计和实现源代码 -FPGA-based SDRAM controller design and implementation source code
mt48lc4m16a2
- 模拟micron的sdram的 VHDL 代码,用于验证自己的sdram控制器。-Micron sdram the VHDL simulation of the code used to validate their sdram controller.
SDRAM-Verilog-HDL
- SDRAM控制器Verilog HDL-source-code.rar-SDRAM-controller-Verilog HDL-source-code.rar
DDR-SDRAM
- 本应用指南描述了在 Virtex™ -4 XC4VLX25 FF668 -10C 器件中实现的 DDR SDRAM 控制器。该实现运用了直接时钟控制技术来实现数据采集,并采用自动校准电路来调整数据线上的延迟。-This application note describes a Virtex ™ -4 XC4VLX25 FF668-10C to implement the DDR SDRAM device controller. The clock control to ach
SDR_SDRAM_IP
- SDR SDRAM 控制器,Altera官网重要资料。内涵说明文档,和VHDL与Verilog两种设计IP。-SDR SDRAM controller from Altera
model
- 用vhdl写的 ddr sdram 控制器,数据位可以修改。在quartus2下仿真通过-With written ddr sdram controller vhdl
4port-sdram
- 4端口SDRAM控制器verilog程序-4-port SDRAM controller with verilog
DDR-SDRAM
- DDR SDRAM的设计,包括DDR SDRAM控制器,以及Modelsim仿真-The design of DDR SDRAM, DDR SDRAM controller, and Modelsim simulation
SDRAM-control-SOPC
- sdram 控制器的sopc搭建 sdram 控制器的sopc搭建 -sdram controller the sopc build sdram controller sopc structures the