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FPGA实现多功能闹钟
- FPGA实现多功能闹钟，有电子钟、秒表、定时器、电子琴功能-FPGA realization of multi-function alarm clock, which can function as a clock, a stopwatch, a timer,and a piano.
VHDL_MIAOBIAO_CODE
- 基于CYCLONE系列FPGA EP1C3T144C8的VHDL秒表代码-CYCLONE series based on the FPGA EP1C3T144C8 stopwatch VHDL code
stopwatch
- 基于fpga的停表设计vudl编写，使用vhdl编写的.v文件。-the stopwatch based on fpga written with vhdl
second
- 基于FPGA的秒表设计 基于FPGA的秒表设计-FPGA-based FPGA design is based on the stopwatch stopwatch stopwatch design FPGA-based design
paobiao
- 一个基于FPGA的数字跑表系统的设计，最小单位是百分表位。采用十进制进位。-FPGA-based digital stopwatch system design, the smallest unit is a digital dial indicator. Binary using the metric system.
stopwatch
- Quartus II工程压缩文件，是一个典型的基于FPGA的秒表工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based project of the stopwatch, a 50MHz frequency, counting, decoding modules. Using VHDL language.
stopwatch
- The program is written in verilog to accomplish functions of a stopwatch. It can be implemented in Xilinx FPGA spartan 3 board.
STOPWATCH
- 是基于FPGA/CPLD的跑表程序，可以存储记录多个运动员的跑步时间，是利用VHDL语言编写的，可以有助于学习EDA技术，可以参考学习，可以帮助你完成VHDL语言的课程设计。-Is based on FPGA/CPLD s stopwatch program, many athletes can store records of running time, is the use of VHDL language, and can help to learn EDA, can refer to t
code
- 这是一个数字跑表的代码，用FPGA实现的，对大家或许有用-This is a digital stopwatch in the code, FPGA implementation, perhaps all of us
stopwatch
- 基于FPGA用VERILOG编写的一个跑表程序....可以实现四位计数跑表-FPGA-based preparation of a stopwatch with a VERILOG program .... can achieve four counts stopwatch ...
Stopwatch
- Stop-watch for FPGA on 7 segment display
vhdl-dianziwannianli
- 基于FPGA的电子万年历，此电子万年历系统主要有8个模块分别设计1. 主控制模块 maincontrol 2. 时间及其设置模块 timepiece_main 3. 时间显示动态位选模块 time_disp_select 4. 显示模块 disp_data_mux 5. 秒表模块 stopwatch 6. 日期显示与设置模块 date_main 7. 闹钟模块 alarmclock 8. 分频模块 fdiv -FPGA-based electronic calen
electronic-clock
- Verliog HDL数字系统设计项目，电子钟。该电子钟可以实现时钟、日期、闹钟、秒表功能。-Verliog HDL digital system design projects, electronic clock. The clock can clock, date, alarm clock, stopwatch function.
FPGA-clock
- 用FPGA编写程序实现数字时钟的设计，具有计时、秒表及闹钟功能-FPGA programming with digital clock design, with timing, stopwatch and alarm functions
stopwatch
- 在fpga上实现秒表计数器的设计，主要目的是实现对fpga基本的认识-Stopwatch counter on the fpga design, the main aim is to achieve understanding of the basic fpga
stopwatch-shuzipabiao
- 在FPGA下实现分频、计数、显示功能。 数字跑表-Divider in FPGA, counting and display functions. Digital stopwatch
VHDL-stopwatch-reports-and-code
- 用VHDL实现数字秒表的设计实践，并用FPGA下载进行功能验证！-Using VHDL the digital stopwatch design practice, and functional verification of FPGA download!
stopwatch-by-verilog-HDL
- 一个基于FPGA用verilog HDL 编写的数字秒表已经LED灯的配合-LED lamp with a digital stopwatch has been prepared based on the FPGA using verilog HDL
A-stopwatch-based-on-FPGA
- 基于FPGA的VHDL语言编写的秒表的源程序，需要在FPGA的平台下进行仿真。-A stopwatch written in VHDL language based on FPGA
STOPWATCH
- STOPWATCH FPGA SEVEN SEGMENT DISPLAY