this contains the impementation of 5 stage superscalar piepline in verilog

实现了简单的CPU功能 采用三级流水线和超标量-CPU functions to achieve a simple three-stage pipeline and superscalar

一款Alpha指令集的超标量处理器的Verilog源码，是学习乱序处理器的难得资料。-A superscalar Alpha processor instruction set of the Verilog source code for a processor to learn valuable information out of order.