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w78e51bcn
- W78E51B 规格书 W78E51B 是宽频率范围、低功耗的8 位微控制器。它的指令集同标准8051 指令集完全兼容。W78E51B 包含4K 字节的Flash EPROM；128 字节的RAM；4 个8 位双向、可位寻址的I/O 口；一个附加的4 位 I/O 口P4；2 个16 位定时/计数器；一个硬件Watchdog 定时器及一个串行口。这些外围设备都由有7 个中断源和2 级中断能力的中断系统支持。为了方便用户进行编程和验证，W78E51B 内含的Flash EPROM
caiji1
- 利用两个双口ram做的乒乓操作，采集高速大容量数据，fpga写，arm读-Two dual-port ram to do the ping-pong operation, collecting high-speed large-capacity data, fpga write, arm reading
aduc812
- ADuC812是美国AD公司推出的高性能单片机，具有集成度高、资源丰富等特点。 (1) 基于8051的内核，指令系统与8051兼容，额定工作频率12MHz。 (2) 8KB片内闪速/电擦除程序存储器 640B片内闪速/电擦除数据存储器 256B片内数据RAM。 (3) 3个16位的定时器/计数器 32根可编程I/O线 9个中断源，2个优先级。 (4) 1个8通道，高精度12位ADC 2个12位电压输出DAC。 (5) 1个片内温度传感器。 (6) 采用3V、5V电压工作
ram_of_Fusion
- Fusion中的双口RAM编写，可以实现双向的调用。用Verilog编写。-Fusion in the preparation of dual-port RAM, you can realize a two-way call. Prepared using Verilog.
FPGA-TWO-RAM
- 这样就可以在FPGA内实现双口RAM了-This can be achieved in the FPGA dual-port RAM
fpga.fifo
- 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the
dualportramtest
- 采用两片AT89S51对双口RAM IDT7132测试程序，采用串口助手显示接收内容。-AT89S51 using two dual-port RAM IDT7132 of testing procedures, the use of serial port to receive the contents of aides show.
two_port_ram
- 介绍如何使用ProASIC3/E的Two Port RAM，从例化到下载测试的整个过程。-Describes how to use the ProASIC3/E of Two Port RAM, to download the test from the cases of the whole process.
USBMeasureAndControl
- 基于USB的数据采集系统，使用两个8051控制和双端口RAM,包含电路设计原理图-USB-based data acquisition system, using two 8051 control and dual-port RAM, including circuit schematics
Two_port_RAMa
- Mactel公司的TWO PORT RAM的详细使用指南，通过具体的实例，解释的特别清楚，对于使用actel公司的fpga芯片来说帮助很大！-TWO PORT RAM Mactel' s detailed user guide, through specific examples to explain the particularly clear, for use actel fpga chip company is very helpful!
dual_port_rom
- dual port ram, it is having two data lines and two address lines at a time we can access two data from the two data lines
DualPortRam
- A systemc implementation of dual port ram module. A vcd file as the sample result is also included. There is a generator for reading/writing data from/to the two ports of the RAM, the tracing of which is offered using the sc_trace API.
Two_Port_RAM
- FPGA libero环境下 介绍ProASIC3/E的TWO Port RAM的使用-FPGA libero circumstances described ProASIC3/E use of TWO Port RAM
Package
- Package consists of two pdf files: i)cdr project: theory and implementation of vhdl ii)I2C bus controller: xilinx implementation of uC interface on CPLD Package consists of 7 vhdl files: string_detector: detects the continuous string of 11
ram_2
- 简易双口ram，使用两个ram ip core，一个写的同时另一个读，并且包含按键使能和数码管以及流水灯显示-Simple dual-port ram, two ram the ip core, a write while another read, and contains buttons to enable digital pipe and the water light show
AdualportramtT
- 采用两片AT89S51对双口RAM IDT7132测试试程序，采用串口助手显示接收内容。， -Using the two AT89S51 dual-port RAM the IDT7132 test pilot program, the serial assistant receive content. ,
6
- 左单片机读取双口RAM中分配给右单片机的配置信息存储空间，右单片机读取双口RAM中分配给左单片机的配置信息存储空间，良但片即读取配置信息后可以按照配置信息对自身工作方式等进行设定，达到双机通信的目的，间接实现了一单片机对另一单片机的配置控制。-Left microcontroller reads the dual-port RAM allocated to the right microcontroller configuration information storage space, rig
ram
- 此文档为fpga控制双口RAM的开发文档，讲解很细，易于上手.双口RAM是在1个SRAM存储器上具有两套完全独立的数据线、地址线和读写控制线，并允许两个独立的系统同时对其进行随机性访问的存储器，即共享式多端口存储器。-This document is controlled dual-port RAM fpga development documents, explain very small, easy to use. Dual-port RAM is an SRAM memory has tw
asyn_fifo
- 本文同步FIFO为TPRAM（两端口RAM，一读一写）。有详细verilog 程序以及说明-FIFO divided by clock domain can be divided into synchronous and asynchronous FIFO FIFO, FIFO read and write only one clock synchronous, asynchronous FIFO read and write were a clock. FIFO divided by
ug_ram_rom
- This user guide describes the Altera megafunction IP cores that implement the following memory modes: ■ RAM:1-Port—Single-port RAM ■ RAM:2-Port—Dual-port RAM ■ ROM:1-Port—Single-port ROM ■ ROM:2-Port—Dual-port ROM Altera provides two IP c