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树式除法型开方器VERILOG实现
- 树式除法型开方器VERILOG实现,用于任意长度的无符号数的开方运算,Square root of the tree-type divider-type device to achieve VERILOG
Verilog-float-mutiplier
- 32位浮点型乘法器，和开方器,很有用的一种，就是认真读懂-32 float mutiplier
Kaifang
- 利用ISE编写的实现开方功能的verilog程序，利用了CORDICIP核，可以完成开方功能-Prepared using ISE verilog program to achieve prescribing functions, using the CORDICIP nuclear, prescribing functions to be completed
sqrt_for_single_float_point
- 用verilog实现了基于中值定理求解单精度浮点开方的功能，希望对大家学习有所帮助-With verilog implemented based on the mean value theorem to solve single-precision floating point square root function, we want to study and help ... ...
sqrt
- 用verilog语言实现二进制数开方运算-verilog sqrt
FPGA-kaifang
- fpga 开方，用verilog语言实现，完成开方运算，方便好用-fpga kaifang，verilog langlange
sqrt
- VERILOG描述的开平方模块核，开方运算是FPGA或ASIC设计中所需要的核心运算模块。-VERILOG descr iption of open square modules nuclear root operation is the core computing module FPGA or ASIC design.
Fast_SQRT
- 只使用简单的移位操作对32bit整型数进行开方的算法的Verilog实现-realize the sqrt algorithm which only use shift operation on 32bit int by Verilog
cordic
- 基于verilog HDL的cordic算法FPGA实现。省去繁琐的乘法开方计算。IDE为vivado 2014( U57FA u4E8Everilog HDL u7684cordic u7B97 u6CD5FPGA u5B9E u73B0 u3002 u7B1 u53BB u7E1 u7410 u7684 u4E58 u6CD5 u5F00 u65B9 u8BA1 u7B97 u300BIDE u4E3Avivado 2014)