搜索资源列表
m序列
- Verilog编写的M序列发生器，希望能对大家带来帮助。 -Verilog prepared by the M-sequence generator, we hope to bring help.
PN_Generator.rar
- 用Verilog编写的一个简单的产生伪随机序列的代码（m序列），比较实用。,Verilog prepared with the emergence of a simple pseudo-random code sequence (m sequence), more practical.
mp3decoder.rar
- mp3 解码的verilog代码，通过仿真综合及验证，能够播放所有的.mp3文件。压缩包包括所有的verilog源码以及详细的文档。,mp3 decoding Verilog code, the adoption of an integrated simulation and verification, can all play. mp3 file. Compressed packet including all the Verilog source code and detailed docu
learn_RS_coding
- 自己根据网上已有程序改写的(127,115)RS编码，有详细的注释及对FPGA实现算法的改写(参考try123.m)，希望可以让大家少走弯路-(127,115) rs encoder/decorder with detailed annotations.
hamming_encodeadecode
- 用Verilog语言编写的对m序列进行汉明码编译码的程序。具体实现为产生m序列后对其进行(7,4)汉明码编码并加错，然后将其纠错译码并输出，详细过程见仿真。-Written by Verilog m sequence of procedures for coding and decoding Hamming codes. Concrete realization of m sequence to produce its (7,4) hamming code and a mistake, and
signalprocess_fft_VHDL
- 一篇用VHDL实现快速傅立叶变换的论文，包括原理分析和代码实现，印度圣雄甘地大学M.A.学院提供，同时包含使用手册，做FFT很好的-VHDL with a fast Fourier transform papers, including the principle of analysis and code, India Mahatma Gandhi Institute of the University of MA, at the same time contains the user manu
shifter
- 移位运算器SHIFTER 使用Verilog HDL 语言编写，其输入输出端分别与键盘/显示器LED 连接。移位运算器是时序电路，在J钟信号到来时状态产生变化， CLK 为其时钟脉冲。由S0、S1 、M 控制移位运算的功能状态，具有数据装入、数据保持、循环右移、带进位循环右移，循环左移、带进位循环左移等功能。 CLK 是时钟脉冲输入，通过键5 产生高低电平M 控制工作模式， M=l 时带进位循环移位，由键8 控制CO 为允许带进位移位输入，由键7 控制:S 控制移位模式0-3 ，由键6 控制
BasicRSA_latest.tar
- RSA ( Rivest Shamir Adleman )is crypthograph system that used to give a secret information and digital signature . Its security based on Integer Factorization Problem (IFP). RSA uses an asymetric key. RSA was created by Rivest, Shamir, and Adleman i
verilog_m
- 用verilog生成的m序列，包含四个.v的文件-verilog m sequence
DE2_SD_Card_Audio(Modified)
- 在DE2开发板上实现的SD卡mp3音乐播放器。硬件部分用Verilog语言编写，在Quartus上编译；软件部分用C语言编写，在Nios2上编译运行。-DE2 development board in the realization of the SD card mp3 music player. Hardware using Verilog language, compiled in the Quartus software with C language, compiled to run
md5.tar
- MD5 Hash Verilog code
2
- RFID系统的IEEE的文章，安全协议，认证- In this paper, we first propose a cryptographic authentication protocol which meets the privacy protection for tag bearers, and then a digital Codec for RFID tag is designed based on the protocol. The protocol w
LIP1732CORE_system_mbus_arbiter
- System Verilog M bus arbiter module
mtspeed
- m法t法编码器测速 verilog语言 m法采样时间可调 t法间隔周期可调-m method t method m encoder velocity verilog language law law sampling time interval period adjustable adjustable t
SD_Controller_Verilog
- 该程序包是SD卡/MMC卡控制器SDC的verilog语言包，它包括以下4部分：RTL源代码，测试平台，软件仿真文件，说明文件。-This source package is the SD card and MMC card controler model based on the Verilog language. It has the following 4 parts: RTL language, testbench, software simulating files and help
convert-.m-to-mdl-file
- priority encoder using verilog size is 20kb
Verilog----m
- verilog 编写的m 序列，可以直接使用。-verilog written m-sequence can be used directly.
Advanced Digital Design with the Verilog HDL
- Advanced Digital Design with the Verilog HDL (M.D.Cilett)
m_sequence
- 基于fpga verilog语言生成的m序列。(Generating m sequences based on FPGA)
m-test
- 产生小m序列，用于扩频系统中，仿真测试正确，反馈级数为4(Generating m sequences)