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這是一堆verilog的source code.包含許多常用的小電路.還不錯用.-many verilog source codes, include a lot of small electrocircuit.
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Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, descr iption documents, DDR verilog model and simulation testbench are all included.
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Source codes for verilog fifo for spartan 3
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Verilog, c and asm source codes of the Minimig system, a fpga implementation of the Amiga computer. Version minimig-j used on the Minimig fpga board.
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Verilog, VHDL, c and asm source codes of the Minimig system, a fpga implementation of the Amiga computer. Version minimig-de1/de2 used on the de1 and de2 fpga boards.
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Verilog, VHDL, c and asm source codes of the Minimig system, a fpga implementation of the Amiga computer. Version c-one used on the c-one fpga board.
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DDR SDRAM source verilog source codes
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Verilog Lab Source Codes
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用verilog语言写的同步FIFO设计源代码。-The source codes for syn-fifo using verilog language.
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卷积码和Viterbi译码的源程序，在Xilinx ISE环境下使用Verilog编写，有助于卷积码和Viterbi译码的学习-Convolutional codes and Viterbi decoding of the source, in the Xilinx ISE environment, use of Verilog prepared to help convolutional codes and Viterbi decoding of the study
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the file contains 5 verilog source codes
1. varying pulses
2. DRAM
3. FIFO
4. UART
5. 16 bit divider
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Codes for FFT using Verilog language
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Verilog Source code for arbitrary waveform generator- simple DDS algorithm codes run on Xilinx Spartan-3E fpga to show output on dac pin.
Please see the included report. its really simple to implement. all source code is given.
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the attached programs are source codes of 4-bit ring counter, 16x1 mux, 8x3 priority encoder, 4x16 decoder, full subtractor using two half subtractors
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SPIverilog代码,属于SOC的子模块，SOC片上系统的一个子模块-SPI verilog source codes
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