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easy_to_modelsim
- 这里包含6个modelsim的学习资料，包括了经典教程、答疑和分别针对VHDL、Verilog语言的仿真例程。-This contains six modelsim of learning materials, including the classic tutorial, tutorials, and were aimed at VHDL, Verilog simulation language routines.
VerilogHDL
- Verilog HDL语言，简单易懂的教程，夏文宇的第二版。-Verilog HDL language, easy to understand tutorials, Xia Wenyu the second edition.
FPGAverilogcode
- verilog的学习很重要的教程，有很大的好处。-verilog tutorial learning is important, a great advantage.
VerilogHDLdesign
- verilog的学习很重要的教程，有很大的好处。-verilog tutorial learning is important, a great advantage.
RTL
- verilog的学习很重要的教程，有很大的好处。-verilog tutorial learning is important, a great advantage.
zhouligongVerilog
- 附近为周立功公司的FPGA基于Verilog语言的教程，其中附带了许多例程，特别适合初学者学习-Zhou, who near the company' s FPGA-based tutorials Verilog language, which comes with a lot of routine, especially for beginners to learn
VerilogHDLhuaweirumenjiaochen
- Verilog HDL 华为入门教程.pdf-Verilog HDL
Verilog_HDL
- verilog语言的全面教程，从基础到深入，可以让初学者快速正握verilog语言的编程。-verilog language, comprehensive tutorials, from basic to in-depth, beginners can quickly grasp verilog language is the programming.
Xia-Yu-Wen
- Verilog数字系统设计教程（夏宇闻）-Verilog Digital System Design Tutorial (Xia Yu Wen)
fpga-tutorial-of-Yuwen-Xia
- 夏宇闻老师的Verilog学习教程，很有用哦-XIA Wen teachers Verilog tutorial, very useful oh
modelsimtest
- 里面是一些verilog代码和一些modelsim的教程-There are some verilog code and tutorials modelsim
VerilogHDL-tutorial
- VerilogHDL硬件描述语言教程，较详细的介绍了verilog的基本用法-VerilogHDL hardware descr iption language tutorial, more detailed introduction to the basic usage of verilog
_Verilog-HDL
- Verilog HDL 华为入门教程 PDF格式，详细的讲解，教你入门-Verilog HDL Huawei Tutorial PDF format, in detail, teaching you started
System_Verilog
- system verilog 的教程 希望有用-system verilog tutorial hope that useful
asic_study
- 压缩包中是ASCI学习资料，包括一个台湾中山大学ASIC实验室综合脚本教程，一本springer出版的交大家用system verilog做验证的书，还有一个xilinx论证的XAPP726 - 无线基站基带处理应用中的FPGA的理由。对大家做通信后端设计很有帮助。-ASCI is compressed package learning materials, including a laboratory in Taiwan Sun Yat-ASIC synthesis scr ipts tuto
05_ledtimer
- 数码管显示的时钟,verilog HDL 基础教程-a timer basied on led
07_piano
- altera FPGA 教程 电子琴 verilog 语言 实现-a piano basied on FPGA ! It is a good thing!
11_temperature
- verilog 语言实现的温度计。 FPGA 基本教程-a temperaturer basied on verilog .
08_uart
- verilog 实现 的串口通信。FPGA 基础教程-uart communication project
modelsim-examples
- 这两个examples 的源码是modelsim 自带教程里面最重要的两个！但是其中一个（memory）在大多是安装文件目录下没有，但是又很有用，我找了好久才找到,PDF上说这几个文件在：<modelsim安装目录>\examples\memory\verilog下:dp_syn_ram.v,ram_tb.v,sp_syn_ram.v 但是找过的人都知道，一般的版本下面都没有这个源码。我分享一下，方便大家查找！-These two examples of the source is