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AD[TLC549]
- 进阶实验之AD[TLC549] 采集模拟输入，电压动态显示在数码管，由verilog编写-Advanced experiments AD [TLC549] capture analog input voltage is dynamically displayed on the LED, written by the verilog
dongtaishumaguan
- 用verilog HDL编写的基于fpga的动态数码管显示程序。-Verilog HDL prepared with fpga based digital control of dynamic display program.
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- 在ISE环境里，用verilog语言编写得数码管显示程序，能动态计数-In the ISE environment, use the verilog language digital display program was able to dynamically count
JTD
- 基于verilog的交通灯，倒计时并具有动态显示功能。红灯结束后黄灯闪烁5s,stop为高电平时，数码管闪烁并禁止通行-traffic light with a function of displaying and counting.
AD[TLC549]
- AD[TLC549] ：采集模拟输入，电压动态显示在数码管(用verilog实现)-AD [the TLC549]: the acquisition of the analog input voltage dynamic digital tube (Verilog)
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- 大西瓜FPGA开发板陪赠资料\大西瓜FPGA开发板例程（基础+进阶）\开发板基础实验\开发板基础实验---数码管的动态显示。Verilog -Watermelon FPGA development board to accompany gifts Data \ the watermelon FPGA development board routines (foundation+ Advanced) \ basic experimental development board \ basic ex
anjian-shumaguan-liushuideng
- verilog HDL语言，功能：按键控制，数码管显示多个状态，同时显示动态流水灯-failed to translate
number_mod
- 以verilog设计最大为99数字在2个数码管资源上的显示，采取的方法是同步动态扫描。-Verilog design to a maximum of 99 digits displayed on two digital resources, the approach is synchronous dynamic scanning.
sencond_counter
- 在ise14.7开发环境下，用Verilog编写的秒表程序，其中通过状态机实现数码管的动态显示-In ise14.7 development environment, using Verilog prepared stopwatch program in which the state machine implementation through dynamic digital tube display
seg70
- 适合fpga，verilog初学者。按一定的频率轮流向各个数码管的COM端送出低电平，同时送出对应的数据给各段。以动态扫描方式在8位数码管“同时”显示0 7-According to certain frequency in turn to various digital tube COM client sends out the low level, at the same time to send out the corresponding data to the paragraphs.In