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DDS_VERILOG
- 本例给出了DDS的VERIOG的程序事例,可发生正弦\\余弦等波形,适应与通信方面的硬件实现!-the cases presented DDS VERIOG procedures example, can occur sine \\ cosine wave such as, Adaptation and communications hardware realization!
adder.tar
- veriog实现的128位高速加法器，fpga实现
lms verilog
- lms veriog程序，不错的代码
MAC
- Verilog code for MAC
interleaver
- 实现矩阵交织的Veriog源代码，内含有modelsim测试文件-Veriog interwoven matrix of the realization of the source code files containing the test modelsim
VerilogHDL10-13
- 这是张延伟主编的《Veriog HDL程序设计实例详解》中第10到13章的代码，可直接应用-This is Zhang Wei edited " Veriog HDL programming example explanation" in the first 10 to 13 chapters of the code can be applied directly
8051_verilog
- 8051 IP, 使用veriog实现，在Altera9.0环境下编译通过-8051 IP in verilog, which is verified in Altera9.0 environmen.
Verilog_Simulation
- Verilog simulation 如何用verilog写Test bench末进行仿真-Verilog simulation It describe how to write a test bench in veriog for design simulation.
Verilog
- verilg 教程，学习verilog 非常好的一本书。-A usefull book for veriog learners.
uart
- 用veriolg 语言编写的串口通讯程序，通过FPGA控制串口的通讯。-a veriog program completed on FPGA to contrlo a uart to communicaton with a computer
ass1_2_hamming
- Hamming codes are a class of binary linear codes. They can detect up to two simultaneous bit errors, and correct single-bit errors. In particular, a single-error-correcting and double error detecting variant commonly referred to SECDED.-a) Develop a
1602lcd
- veriog HDL语言实现LCD1602显示-This program can drive the LCD1602 with verilog HDL language
FPGA-traffic-light
- 基于FPGA的交通灯控制器的设计，利用的是verilog HDL 语言。-design of traffic light based on FPGA,use the veriog HDL language.
kp_verilog
- veriog 实现求逆模块 加仿真结果 shi henyong-verilog is useful in finite field
Ssmic13g_hs_nM
- 中芯国际130nm库文件，在DC综合练习中可以使用，并能帮帮助理解库的含义-DC Ｖｅｒｉｏｇ，已通过测试。 -SMIC 130nm library file, you can use in the DC Comprehensive Exercises, and help to help understand the meaning of the library-DC Veriog has been tested.
1-fpga-led
- 利用veriog语言编程，实现fpga板控制led灯点亮-Use veriog language programming, fpga board control led lights
divide
- 用veriog实现的任意位数的除法，在modelism中验证过了已经。-Implementation division with verilog.
std_div
- 分频模块 用veriog hdl实现十六分频-clock division module
Building-Counters-Veriog-Example
- building counters in vhdl
clk-divide5
- 实现5分频计数的veriog电路，简单易懂，欢迎大家下载学习-Achieve 5 divider count veriog circuit, easy to understand, welcome to download the study