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ALU.zip
- VHDL实现cpu核心逻辑与运算单元模块的实现，完成4bit*4bit输入8bit输出的运算，可做加减乘除逻辑移位6种操作,the implementation of Arithmetic and logic unit based on VHDL, can do as the adder,subtractor,multiplier,divider,shifter and logic operation.
vhdl_123
- 几个简单的vhdl程序。包括加法器，减法器，乘除法等等。-A few simple vhdl program. Including the adder, subtractor, multiplication and division and so on.
addersandsubtractors
- this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code c
addersubtractor10
- vhdl coding for adder subtractor used in dct
sm
- This example shows how a Sm component is directly coded in VHDL as concurrent statements. The multiplexor is coded as a single "when" statement. "Sm" is mnemonic for subtractor-multiplexor.
Generic_Adder_Subtractor
- Generic adder subtractor by VHDL
addersubtractor
- it is adder & subtractor in vhdl
VHDL
- 减法器可以完成VHDL的减法功能，还可以组成8为减法器的功能-Subtraction can be done VHDL subtraction function can also be composed of 8 features for the subtractor
example7--21.10.2011
- full adder subtractor 16 bit for vhdl
subtractor
- Sub-tractor using VHDL
VHDL_full_subtractor
- VHDL program_ A 4-bit subtractor by using 4 one-bit full-subtractor
VHDL-CODE-for-adder-and-subtractor
- vhdl code for implementation of adder and subtractor on fpga
excess-3-code-adder-subtructer
- 余3码excess-3 code加法器和减法器，用vhdl实现-I 3 yards excess-3 code adder and subtractor using vhdl
VHDL-Code-For-Full-Subtractor-By-Data-Flow-Modell
- VHDL Code For Full Subtractor By Data Flow Modelling
VHDL-Code-For-Half-Subtractor-By-Data-Flow-Modell
- VHDL Code For Half Subtractor By Data Flow Modelling
floating-point-adder-subtractor
- floating point adder/subtractor in VHDL
Serial-borrow-eight-subtracte
- 本程序实现了串行借位的八位减法器，采用VHDL语言实现。-This program implements eight serial borrow subtractor, using VHDL language.
sub
- subtractor vhdl code for fpga
sub_1
- sub_1 subtractor 1 bit xxxxxxxxxxxx