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eqingdaqi
- VHDL电子抢答器的实现。有多个文件，主控件是用图行实现。其余各功能模块用VHDL实现-VHDL electronic Responder realized. A number of documents, the main controls are using maps the bank. The remaining modules using VHDL
DigitalClockVHDL
- 多功能电子时钟的VHDL源代码。使用MAX+PLUS II进行编译。该文档有详细的说明和程序注释。-VHDL source code. Use MAX PLUS II computer. The document is described in detail in the Notes and procedures.
duogongnengdianzishuzizhong
- 多功能电子数字钟vhdl 计算机专业课程设计必备
vhdl-多功能电子表
- 这是一个用vhdl编的多功能电子秒表，可以记录几个人的时间，并且可以在跑秒的时候查看记录。。〔原创〕-This is a series with VHDL multifunctional electronic stopwatch, can be recorded by several people, and that they could run in the second examined the records. . [Original]
基于verilog HDL语言的电子钟
- 基于verilog HDL语言的电子钟，多功能电子时钟,Verilog HDL language-based electronic bell, electronic multi-function clock
clock
- 多功能电子时钟，具有时间显示，时间调整等功能。-Multi-function electronic clocks, time display, time adjustment functions.
clock
- 时钟的vhdl实现，具有打铃等功能，是一个很好的实现，我们做电子竞赛的源代码-VHDL clock to achieve a play-ling and other functions, is a good realization, we have the source code of the electronic competition
digital_clk
- 该工程的主要功能是由VHDL语言实现多功能数字电子时钟-The project s main function is to achieve by the VHDL language multifunction digital electronic clock
128634vhdl-sirenqiangdaqi
- 多功能电子抢答器vhdl 计算机专业课程设计必备。初学者的好帮手。-Answer vhdl electronic multi-function devices required computer science curriculum design. Good help for beginners.
digitalclock
- 数字电子钟，24时制计时，带有调时功能，对分秒时分别进行调整。-Digital electronic clock, 24 when the system time with when the transfer function, minutes and seconds, respectively to adjust.
watch
- 本文件为电子设计而开发的多功能数字钟VHDL语言完整源代码 --该数字钟实现的功能有时间，秒表，闹钟，年月日的显示设置等 -This document is multi-functional electronic design and development of a complete VHDL, digital clock source code- the digital clock function can be achieved time, stopwatch, alarm clo
SG_FPGA
- 2006年电子设计竞赛二等奖，多功能函数、信号发生器核心器件FPGA内部的原理图，主要模块用VHDL代码描述，包括PLL、相位累加器、波形算法和正弦波查找表，可实现0.005Hz~20MHz的多波形信号产生，频率步进值0.005，输出接100MSPS速率的DAC--AD9762-Electronic Design Competition 2006, second prize, multi-function signal generator within the core of the devic
clock_fpga
- 基于VHDL的FPGA设计，设计一款多功能的电子定时器，包括计时跟倒计时。-VHDL-based FPGA design, design a versatile electronic timers, including the timing with the countdown.