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0下载：
论文格式，内含Viterbi编解码器的完整vhdl代码，文件为.nh格式-paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format
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硕士论文，viterbi译码器的低功耗设计，最后附带源码，VHDL-master's thesis, Viterbi Decoder low-power design, the final collateral source, VHDL
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提供了一个硬判决的viterbi译码器（2，1，3）
有源程序及算法描述，未成定稿，只供参考
（vhdl 语言描述）
-provided a hard decision of the Viterbi Decoder (2,1, 3) the source code and the algorithm descr iption, from his position as final, for reference (vhdl Descr iption Language)
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viterbi译码器的IP核，可以直接编译使用,viterbi decoder IP core, the compiler can directly use
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verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
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用VHDL语言设计维特比 解码器 是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation
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Viterbi译码器的FPGA实现代码,来在国外大学论坛.-Viterbi decoder implementation of the FPGA code to the Forum at foreign universities.
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Viterbi decoder algorithm
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Viterbi译码器的编解码器的设计
用Verilog实现-Viterbi decoder。Verilog
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viterbi decoder implementation
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viterbi decoder with convolutional encoder
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paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format paper format that include s Viterbi Decoder complete VHDL code for the document. Nh format paper format that includes Viterbi Decoder complete VHDL code for the
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vhdl code for viterbi decoder
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verilog code for viterbi encoder and decoder
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NS2网络层仿真的材料,可动态调整发射功率-NS2 network layer simulation of materials, which can dynamically adjust transmit power
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编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法-Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange
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this codes are for convolution encoder and Viterbi decoder synthesis and implementation.
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Vetrbi decoder VHDL code
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viterbi decoder VHDL material
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