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48_order-FIR-filter-with-8-folder
- 该代码是设计一个48阶FIR滤波器的文档，该设计方案主要运用了数字信号处理VLSI实现中的折叠的方式。-The code is a 48-order FIR filter design document, the main use of the design of VLSI implementation of digital signal processing in the way of folding.
DesignofIntegratedCircuitsforOpticalCommunications
- Design of Integrated Circuits for Optical Communications deals with the design of high-speed integrated circuits for optical communication systems. Written for both students and practicing engineers, the book systematically takes the reader from basi
mpeg
- code to implement mpeg in vlsi
UART0_2
- vlsi UART referene, use UART0_3
2008.12.09.ms
- vlsi sensor design and application
High_performance_FFT
- Descr iption of a high performance FFT architecture useful for VLSI implementation.
OFDM_VLSI
- OFDM系统均衡器设计优化及VLSI实现的研究文章-OFDM VLSI
VLSIFFTRadix2forDSP
- VLSI implementation of high speed and high resolution FFT algorithm based on Radix 2 for DSP application
High-speedhighperformanceFFT
- 高速高性能FFT处理器的VLSI实现研究，适合做FPGA的技术人员参考研究FFT-High-speed high-performance FFT processor VLSI realization of research, suitable for FPGA technology reference study FFT
thesis
- thesis related to vlsi area, pll and frequency synthesizer
seminar040227
- Low Power VLSI Design For Multimedia Applications
streamcipherbyvhdl
- describe the vlsi implementation of some stream cipher (RC4,A5/1,helix,E0)
high_speed_architecture_for_reed_solomon_decoder.r
- RS码的解调算法，BM算法(Berlekamp–Massey)和一种新型高速VLSI算法。-High-Speed Architectures for Reed–Solomon Decoders
stickdiagram
- stick diagram of VLSI design
NMOSFebrication
- nmos febrication of VLSI design
SNN4ImageFeaturIPCAT2007
- Based on the information processing functionalities of spiking neurons, a spiking neural network model is proposed to extract features from a visual image. The network is constructed with a conductance-based integrate-and-fire neuron model and a set
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- 高速QAM解调器的算法及VLSI实现研究，费了很大力气才搞到得-QAM modulation is related to the classical algorithm, had made diligent efforts to obtain a
VLSL-Design-of-High-Performance-Full-search-Block-
- 给出了一种用于H.264变换尺寸全搜索快匹配算法的运动估计电路的改进结构，并完成了VLSI设计。通过脉动阵列和全流水线的设计，达到最高的数据重用率、最小的I/O引脚和100 的硬件计算效率。-An improved architecture for H.264 full-pel motion estimation using variable block size full-search block-matching algorithm is proposed in this paper. To
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- 一维离散小波变换的VLSI设计很好的学习资料-One-dimensional Discrete Wavelet Transform VLSI design of good learning materials
fulltext
- VLSI Implementation of Discrete Wavelet Transform using Systolic Array Architecture