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VLSI-test-technology
- 中国科学院计算所李晓维研究员的VLSI测试与可测试性设计讲义
VLSI__TEST
- 中科院研究生院VLSI测试课程课件，VLSI TEST PRINCIPLES AND ARCHITECTURES Design for Testability，搞好测试必看。
VLSI
- VLSI Test Principles and Architectures Design for Testability..... very nice pdf
atalanta
- 基于stack-at fault的超大规模数字集成电路自动测试向量生成算法（ATPG）。输入.bench格式，输出测试向量。-Automatic test pattern generation (ATPG) algorithm for VLSI circuits
circ
- c program to levelise a combinational vlsi circuits in test pattern generation. it will work for iscas 85 benchmark circuits
Chapter-6-ATPG
- about adavance self genersated test sequnce in VLSI
05~chapter-03-lfsim
- Slides from "VLSI test" book.
09~chapter-05-lbist
- Slides from "VLSI Test arch" book
03~chapter-02-dft
- Slides from book "VLSI Test principles"
07~chapter-04-atpg
- Slides from "VLSI test" book.
01~chapter-01-intro
- VLSI Test slides from "VLSI Test arch" book.
test.in
- introduction to vlsi testing
lfsr
- Ruby LFSR 模拟程序。 可以自动生成任意位数的VLSI test pattern用于VLSI TEST. 含有两种lfsr,等概率LFSR和加权LFSR.-LFSR simulator based on ruby language.
SAIFI-VLSI-114
- Low-Power Programmable PRPG With Test Compression Capabilities
Area-Delay-Power-Efficient-Carry-Select-Adder-usi
- Implementation of IEEE 2015 paper for Area–Delay–Power Efficient Carry-Select Adder using VLSI verilog .The code tested by modelsim and also main program is test.v . If have any trouble mail to anandg.embedd@gmail.com-Implementation of IEEE 2015 pape
bist 2017 paper
- A new low-power (LP) scan-based built-in selftest (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministi
Atalanta-M-2.0
- AUTOMATIC TEST PATTERN GENERATION TOOLBOX FOR VLSI TESTING AND FAULT COVERAGE MEASUREMENT
15~chapter 10 bscan 1500
- VLSI test slides - VLSI TEst archiecture book