Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descr ipted in the Constrained file quad.ucf. To use them, y

Project frequency inverter for induction motors very helpful

Xilinx user constraints file for the cpld xc9536 or xc9536xl or xc9572 or xc9572xl