搜索资源列表
IPcore
- 基于EP3C25的Altera SDI IP核的使用-EP3C25 Altera SDI IP
ddc_FPGA
- 简要介绍了数字下变频的设计，通过采用xilinx的ise软件，ipcore的调用实现-Briefly introduced the design of digital down conversion, through the use of ise the xilinx software, ipcore call the realization of
ipcore
- XILINX公司ISE自带的IP核，功能介绍，如何使用这些IP核来加快你的开发。-IP release note guide
standard_sim_tb
- xilinx CTC IPcore(encoder 和 decoder）的标准测试，未经信道加噪-the standard test of xilinx CTC IPcore (encoder and decoder) , without the channel with noise
hwitl_sim
- xilinx CTC IPcore(encoder 和 decoder)的测试，经过AWGN信道。 -This simulation uses a AWGN module to include noise as part of the simulation. Prior to running the simulation, the UniSim models for the encoder and decoder must be generated as well as the AWGN
ctc_advanced_sim_tb
- xilinx CTC IPcore 误码率测试-xilinx CTC IPcore Bit Error Rate Test
2440Program
- ARM 2440的操作系统与IPcore 设计-ARM 2440 operation system and IPcore
Xilinx
- Xilinx12.3和12.4 license 加强版支持更多ipcore 以及modelsim编译ise 库的方法说明-Xilinx12.3 and 12.4 license as well as enhanced support for more ipcore modelsim compile ise descr iption of the ways library
ddr2_mem
- DDR2 xilinx ipcore 头文件 可以进行读写DDR2操作的接口! 读写时注意 按照时序控制进行！-DDR2 xilinx top file， you can read or write DDR2 interface。 attention：please control it ！
Xilinx_DDR2_IP_TEST
- 本文档对Xilinx 公司FPGA开发环境中ISE中如何调用DDR2 IP进行了详细的说明。直接例化IPCORE,采用无TESTBENCH，无PLL的方式.-This document FPGA from Xilinx ISE development environment how to call DDR2 IP for a detailed descr iption. Direct instantiation IPCORE, no-TESTBENCH, no PLL ways.
FIFO_TEST
- XILINX FIFO IP核测试程序，已经通过测试，方便可用-XILINX FIFO IPcore testbench
microblaze_GPIO
- 基于xilinx 的软核microblaze的GPIO IP核程序(GPIO IPcore program for soft core MicroBlaze based on Xilinx)